The aim of this paper is to present a flexible and open-source multi-scale simulation software which has been developed by the Device Modelling Group at the University of Glasgow to study the charge transport in contemporary ultra-scaled Nano-CMOS devices. The name of this new simulation environment is Nano-electronic Simulation Software (NESS). Overall NESS is designed to be flexible, easy to use and extendable. Its main two modules are the structure generator and the numerical solvers module. The structure generator creates the geometry of the devices, defines the materials in each region of the simulation domain and includes eventually sources of statistical variability. The charge transport models and corresponding equations are implemented within the numerical solvers module and solved self-consistently with Poisson equation. Currently, NESS contains a drift–diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) solvers. The NEGF solver is the most important transport solver in the current version of NESS. Therefore, this paper is primarily focused on the description of the NEGF methodology and theory. It also provides comparison with the rest of the transport solvers implemented in NESS. The NEGF module in NESS can solve transport problems in the ballistic limit or including electron–phonon scattering. It also contains the Flietner model to compute the band-to-band tunneling current in heterostructures with a direct band gap. Both the structure generator and solvers are linked in NESS to supporting modules such as effective mass extractor and materials database. Simulation results are outputted in text or vtk format in order to be easily visualized and analyzed using 2D and 3D plots. The ultimate goal is for NESS to become open-source, flexible and easy to use TCAD simulation environment which can be used by researchers in both academia and industry and will facilitate collaborative software development.
We investigated the device performance of the optimized 3-nm gate length (L G ) bulk Silicon FinFET device using 3-D quantum transport device simulation. By keeping source and drain doping constant and by varying only the channel doping, the simulated device is made to operate in three different modes such as inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode. The excellent electrical characteristics of the 3-nm gate length Si-based bulk FinFET device were investigated. The sub threshold slope values (SS~65mV/dec.) and drain-induced barrier lowering (DIBL<17mV/V) are analyzed in all three IM, AC and JL modes bulk FinFET with |V TH | ~0.31 V. Furthermore, the threshold voltage (V TH ) of the bulk FinFET can be easily tuned by varying the work function (WK). This research reveals that Moore's law can continue up to 3-nm nodes.
Silicon (Si) and Germanium (Ge) ultrathin body junctionless field-effect transistor (UTB-JLFET) with L G = 1 nm and L G = 3 nm were demonstrated by solving the coupled drift-diffusion and density-gradient model. The simulation results show that the Si and Ge channel can be used in ultrashort channel device as long as UTB is employed. As UTB is employed, ultrashort channel device does not need to follow an empirical rule of T ch = L G /3. Furthermore, Ge UTB-JLFET 6T-SRAM cell has reasonable static noise margin value of 149 mV. The circuit performances reveal that UTB-JLFET can be used for sub-5-nm CMOS technology nodes. Index Terms-Junctionless FET (JLFET), ultra-thin body (UTB), germanium.
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