The physical analysis on electrical junction of junctionless FET

Chen, Lun-Chun; Yeh, Mu-Shih; Lin, Yen-Wei; Lin, Ko‐Wei; Wu, Mengqi; Thirunavukkarasu, V.; Wu, Yu‐Chung

doi:10.1063/1.4975768

Cited by 13 publications

(8 citation statements)

References 6 publications

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“…In addition, the current at Vgt=Vgb=0 V is extracted to determine the on-off current ratio. As known in Figure 2(a), the threshold voltage increases from 0.54 V to 0.72 V, and the on-off current ratio increases about 450 times from 2.8×10 4 to 1.27×10 7 when the relative permittivities of the upper and lower gate oxide increase from k1=k2=3.9 to k1=9 and k2=25. It can be found 3885 that the increasing of power dissipation due to the increase in the threshold voltage can not only be offset by the increase in the on-off current ratio but also can be greatly reduced.…”

Section: The On-off Current and Threshold Voltage Of The Asymmetrical Jldgmentioning

confidence: 68%

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

Jung

Kim

2021

IJECE

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The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO2/high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 104 or less is shown for SiO2, but the on-off current ratio for TiO2 (k=80) increases to 107 or more.

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Section: The On-off Current and Threshold Voltage Of The Asymmetrical Jldgmentioning

confidence: 68%

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

Jung

Kim

2021

IJECE

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“…The subthreshold swing is defined as the change of the top gate voltage to the logarithmic value of the drain current and is expressed as follows. In the case of the JLDG MOSFET, most of the drain current moves along the central axis, so x = xmin and y = tsi/2 are substituted into (5) to obtain the ∂ / [26]. As a result, the subthreshold swing model of (6) can be obtained from (4) and (5).…”

Section: The Subthreshold Swing Model Of the Asymmetric Jldg Mosfetmentioning

confidence: 99%

“…In the case of the JLDG MOSFET, most of the drain current moves along the central axis, so x = xmin and y = tsi/2 are substituted into (5) to obtain the ∂ / [26]. As a result, the subthreshold swing model of (6) can be obtained from (4) and (5). The xmin is selected as the position having the minimum potential among the potential distributions of y = tsi/2.…”

Section: The Subthreshold Swing Model Of the Asymmetric Jldg Mosfetmentioning

confidence: 99%

“…Major semiconductor manufacturers are investing enormous funds in reducing transistor size [1][2][3]. The device developed to overcome the short channel effect and the difficulty of the process inevitably caused by the size reduction of the transistor is a junctionless double gate JLDG MOSFET [4][5][6][7]. In this structure, there is no abrupt change of doping distribution between the source/drain and the channel, so it is easy to process and reduce the degradation of the subthreshold swing, threshold voltage shift, and drain induction barrier lowering (DIBL) caused by the transistor size reduction [8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

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Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

Jung

2021

IJECE

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

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“…However, the scaling of conventional planar transistor has reached its limit which lead to increase in short channel effects (SCEs) and sensitivity to process variation [2]. SCEs are the main limitations in the scaling of MOSFET below 10nm [3]. SCEs comprises of Drain Induced Barrier Lowering (DIBL), subthreshold slope (SS), limitation imposed on electron drift characteristics in the channel, increase in threshold voltage variation, reduction in ION/IOFF ratio and increase of leakage current causing the scaling of conventional CMOS transistors in sub 10nm technologies almost impossible.…”

Section: Introductionmentioning

confidence: 99%

Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics

Sule¹,

Ramakrishnan

Alias

et al. 2020

IJEEI

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Metallurgical junction and thermal budget are serious constraints in scaling and performance of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). To overcome this problem, junctionless nanowire fieldeffect transistor (JLNWFET) was introduced. In this paper, we investigate the impact of device parameter variation on the performance of n-type JLNWFET with high-k dielectrics. The electrical characteristic of JLNWFET and the inversion-mode transistor of different gate length (LG) and nanowire diameter (dNW) was compared and analyzed. Different high-k dielectrics were used to get an optimum device structure of JLNWFET. The device was simulated using SDE Tool of Sentaurus TCAD and the I-V characteristics were simulated using Sdevice Tools. Lombardi mobility model and Philips unified mobility model were applied to define its electric field and doping dependent mobility degradation. A thin-film heavily doped silicon nanowire with a gate electrode that controls the flow of current between the source and drain was used. The proposed JLNWFET exhibits high ON-state current (ION) due to the high doping concentration (ND) of 1 x 10 19 cm -3 which leads to the improved ON-state to OFF-state current ratio (ION/IOFF) of about 10% than the inversionmode device for a LG of 7 nm and the silicon dNW of 6 nm. Electrical characteristics such are drain induced barrier lowering (DIBL) and subthreshold slope (SS) were extracted which leads to low leakage current as well as a high ION/IOFF ratio. The performance was improved by introducing silicon dioxide (SiO2) with high-k dielectric materials, hafnium oxide (HfO2) and silicon nitrate (Si3N4). It was found that JLNWFET with HfO2 exhibits better electrical characteristics and performance.

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The physical analysis on electrical junction of junctionless FET

Cited by 13 publications

References 6 publications

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics

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