Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics

Abstract

Metallurgical junction and thermal budget are serious constraints in scaling and performance of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). To overcome this problem, junctionless nanowire fieldeffect transistor (JLNWFET) was introduced. In this paper, we investigate the impact of device parameter variation on the performance of n-type JLNWFET with high-k dielectrics. The electrical characteristic of JLNWFET and the inversion-mode transistor of different gate length (LG) and nanowire diameter (dNW) was compared and analyzed. Different high-k dielectrics were used to get an optimum device structure of JLNWFET. The device was simulated using SDE Tool of Sentaurus TCAD and the I-V characteristics were simulated using Sdevice Tools. Lombardi mobility model and Philips unified mobility model were applied to define its electric field and doping dependent mobility degradation. A thin-film heavily doped silicon nanowire with a gate electrode that controls the flow of current between the source and drain was used. The proposed JLNWFET exhibits high ON-state current (ION) due to the high doping concentration (ND) of 1 x 10 19 cm -3 which leads to the improved ON-state to OFF-state current ratio (ION/IOFF) of about 10% than the inversionmode device for a LG of 7 nm and the silicon dNW of 6 nm. Electrical characteristics such are drain induced barrier lowering (DIBL) and subthreshold slope (SS) were extracted which leads to low leakage current as well as a high ION/IOFF ratio. The performance was improved by introducing silicon dioxide (SiO2) with high-k dielectric materials, hafnium oxide (HfO2) and silicon nitrate (Si3N4). It was found that JLNWFET with HfO2 exhibits better electrical characteristics and performance.

Study ofImpact of HfO2gate oxide on the Electrical Characteristics of Nanowire Junction lessTransistor

“…Reduction of the performance, I ON /I OFF ratio of the transistors, causes unsteadiness of transistor device and limits subthreshold circuit design. Similarly, when a leakage current increased, the static power consumption also increased [2,3].…”