This paper describes the architecture and implementation of a novel voltage controlled oscillator based analogto-digital converter (VCO-ADC). Instead of a ring oscillator (RO), the VCO is built with a pulse frequency modulation (PFM) architecture where an analog feedback loop ensures both oscillation and linearity of the voltage-to-frequency conversion. A multibit first-order noise-shaped output is achieved by sampling a digital delay line that acts as a part of the oscillator and as a multibit quantizer. A prototype has been implemented in a 40nm CMOS process. Although most of the circuit elements are taken from a standard digital library, a transconductor is required as input stage. To ensure proper linearity, a bulk-driven transconductor has been designed. The ADC measurements reach 53 dB of SNDR at 1 GHz sampling frequency in a 20 MHz bandwidth with a pseudo-differential architecture. Powered at 1.1 V, the power consumption is 3.5 mW. The active area is 0.08 mm 2 . The resulting FoM equals 242 fJ/step.
A 10 bit 8 MS=s cyclic ADC without a dedicated sample and hold is presented. Op-amp sharing and a single ended reference buffer loaded with a resistive divider are used. For power saving the common-mode buffer was replaced by a simple low pass filter. The ADC consumes 4.5 mW and occupies 0.145 mm 2 . It is fabricated in a 130 nm 1.2 V CMOS process and achieves 57 dB SNDR for an 11 MHz input. The cyclic stage works with a 40 MHz clock which can be increased to 65 MHz where the effective number of bits is reduced to 8. A novel dynamic current switching technique is introduced to reduce the power consumption by 20%. The figure of merit (FOM) is about 0.37 pJ=conversion step.Ein 1,2 V 4,5 mW 10 bit 8 MS=s zyklischer ADC f € u ur mobiles Video und Sensoranwendungen. In diesem Beitrag wird ein 10 bit 8 MS=s zyklischer ADC ohne Abtast-und Halteglied pr€ a asentiert. Durch gemeinsame Ben€ u utzung eines Verst€ a arkers und eines unsymmetrischen Entkopplers, welcher mit einem resistiven Spannungsteiler belastet wird, wird Leistung gespart. Um weiter Leistung zu sparen, wurde der Gleichtaktverst€ a arkter durch ein einfaches Tiefpass-Filter ersetzt. Der ADC verbraucht 4,5 mW und beansprucht eine Fl€ a ache von 0,145 mm 2 . Dieser ADC wurde in einem 130 nm 1,2 V CMOS-Prozess gefertigt und erreicht ein Signal zu Rausch-und Verzerrungsabstand von 57 dB f€ u ur ein 11-MHz-Signal. Die zyklische Stufe arbeitet mit einem 40-MHz-Takt, welcher bis 65 MHz erh€ o oht werden kann, wobei die effektive Anzahl der Bits auf 8 reduziert wird. Ein neues dynamisches Stromschaltverfahren wird vorgestellt, welches den Stromverbrauch um 20 % reduziert und einen G€ u utefaktor von 0,37 pJ erm€ o oglicht. Schl€ u usselw€ o orter: portables Video; mobiles Video; zyklischer ADC; niedrige Leistung; gemeinsame Ben€ u utzung eines Verst€ a arkers
A 10 bit 165MS/s pipelined ADC without a dedicated sample and hold is presented. Op-amp sharing and a single ended reference buffer loaded with a resistive divider are used. The ADC consumes 56mW and occupies 0.15 mm 2 . It is fabricated in a 90nm 1.2V CMOS process and achieves 55 dB SNR for a 60 MHz input. A novel measurement technique called "pad noise suppression" is introduced to prevent digital crosstalk from data outputs.
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