Low-voltage CMOS technologies pose new problems in the design of multibit continuous-time sigma-delta modulators. One of these problems is the implementation of the coarse quantizer with an array of voltage comparators. This work presents a novel architecture of multibit continuous-time sigma-delta modulator that employs a time encoding quantizer and irregular sampling instead of a flash analog-to-digital converter. The time-encoding quantizer is based in a modulated oscillator that produces a two-level signal. A digital decoder converts the binary signal into an irregularly sampled multibit signal that is interpolated and fed back into the loop filter of the sigma-delta modulator. This architecture is especially adequate for low-voltage technologies due to the absence of a resistive reference ladder in the quantizer and may permit a significant reduction of the complexity of the existing continuous-time sigma-delta modulators.

Presented is a new ADC topology based on an asynchronous PWM modulator followed by a VCO and a counter. The PWM modulator first encodes the analogue input into a binary waveform. Then, the VCO implements a multibit first-order noise shaping modulator, sampling and quantising the input signal encoded by the PWM modulator. With this architecture, the linearity of the whole converter is independent of the VCO linearity as the VCO is modulated by a two valued signal only. Proposed is a hardware implementation suitable for low power applications that does not require linear amplifiers.Introduction: Continuous time sigma delta (CTSD) analogue-to-digital converters (ADCs) require a first integrator that is ultimately responsible for the performance of the overall converter. This first integrator is usually implemented with a CMOS operational amplifier that consumes a large silicon area and a significant part of the power budget to achieve gain and linearity. For this reason, there has been a search for new topologies that permit mostly digital ADC implementations. One of these topologies is based on a voltage controlled oscillator (VCO) [1], which provides a multibit quantised output with a simple ring oscillator but at the expense of uncompensated distortion due to the nonlinear voltage-to-frequency conversion of the VCO. On the other hand, pulse width modulation (PWM) has been used to implement efficient ADCs but still requiring either linear integrators [2] or a power consuming time to digital converter (TDC) [3]. In this Letter, we present an architecture that combines both the VCO and the PWM approaches to implement a converter that mitigates the nonlinearity problems of VCOs without requiring high performance operational amplifiers.

The receiver architecture proposed in this brief seizes the subsampling properties of continuous-time sigma-delta (61) modulators based on distributed resonators to construct a quadrature receiver. The proposed architecture is based on a low-pass 61 modulator that subsamples an intermediate frequency signal around the sampling frequency and does not require quadrature mixers. Instead, the quadrature mixing is replaced by suitably choosing the sampling instants inside the loop. Two practical circuit implementations are proposed. The first one uses separate circuitry for the and paths. The second architecture introduces an innovative way to produce the and outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The proposed modulator may be feasible for the typical IF frequencies used in cellular base stations.

The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 µm CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm2, which means a pressure resolution of 1 Pa, while consuming 146 µA from a 1.5 V power supply.