A 1.2V 56mW 10 bit 165Ms/s pipeline-ADC for HD-video applications

Abstract

A 10 bit 165MS/s pipelined ADC without a dedicated sample and hold is presented. Op-amp sharing and a single ended reference buffer loaded with a resistive divider are used. The ADC consumes 56mW and occupies 0.15 mm 2 . It is fabricated in a 90nm 1.2V CMOS process and achieves 55 dB SNR for a 60 MHz input. A novel measurement technique called "pad noise suppression" is introduced to prevent digital crosstalk from data outputs.