A 150-200°C atomic layer deposition (ALD) process has been developed for advanced gap and tunnel junction applications for thin films heads. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along the sidewall. This process provides smooth false(Rnormala≃2Åfalse), pure (impurities <2 atom %), AlOx films with excellent breakdown strength (9-10 MV/cm). The process uses trimethylaluminum (TMA) as the aluminum source and water as the oxidant. The optimal precursor/oxidant delivery methods for high breakdown strengths were found to be vapor draw for the TMA and a bubbler for the water. For both reagents, a sweep gas is used to reduce the transit time to the wafer. The ALD AlOx films are continuous and exhibit excellent insulating characteristics even down to 5-10 Å making them a potential candidate for tunnel barriers for magnetic tunnel junctions. By plasma annealing the films in situ every 25-50 Å, the as-deposited tensile stress becomes slightly compressive and the breakdown field exceeds 10 MV/cm. ALD provides a relatively low deposition rate of 0.8 Å/cycle. A small chamber volume that allows the cycle time of 5 s is the key to meeting production throughput requirements of 4-6 w h−1 for a 100 Å film. © 2001 The Electrochemical Society. All rights reserved.

The use of copper interconnects enables higher speed, enhanced electromigration lifetime reliability, reduced power consumption, and ultimately reduced manufacturing cost for silicon integrated circuits. The formation of planarized inlaid copper interconnects requires sequential deposition of a continuous diffusion barrier layer followed by copper seed/fill deposition and chemical-mechanical polishing (CMP). In this article we present a vacuum-integrated cluster tool technology for deposition of a TaN barrier and copper seed/fill layers using metalorganic chemical vapor deposition (MOCVD). The MOCVD-based TaN layers deposited at substrate temperatures below 430 °C are highly conformal, have 800–1000 μΩ cm resistivity, have satisfactory adhesion to silicon dioxide, and provide superior diffusion barrier properties compared to Ta and TaN layers deposited by physical vapor deposition. The cluster MOCVD-Cu process is capable of depositing conformal and low-resistivity copper seed layers with satisfactory adhesion for subsequent copper filling by either electrochemical deposition or MOCVD. The cluster MOCVD technology has been used to fabricate inlaid copper metallization lines and plugs based on CMP damascene processing. The combination of MOCVD TaN and MOCVD copper is expected to provide an extendable multigenerational copper metallization solution for 0.18–0.10 μm technology nodes and beyond.

The insertion of single-wafer thermal and CVD technologies into the front- and back-end of the line processing starts with study of the integrated circuits manufacturing and device performance requirements. Relying upon the lessons learned and using the concurrent engineering approach, next generation processing equipment design architecture is then defined. In order to meet the process performance, throughput, and cost of ownership requirements of semiconductor IC manufacturing as defined in the SIA road map, heavy emphasis must be put on sensor fusion and model-based process control. In the existing semiconductor IC manufacturing equipment, process control is usually accomplished by control of equipment settings, qualification wafer runs and ex-situ measurements of the various wafer properties, as well as design architecture for stable equipment performance. The conventional approach, however, suffers from slow drifts of various equipment state parameters such as infrared absorbing quartz media causing thermal memory effects, or deposition of films on the reactor walls causing variation in the optical characteristics of the reactor as well as chemical and particle memory effects. Using model-based real-time control in conjunction with implementation of various in-situ and ex-situ sensors, these effects can be well monitored and controlled. This paper is to discuss various production related issues with single-wafer thermal and CVD technologies.

A Universal Thermal Module™ (UTM™) has been developed for vacuum-integrated cluster RTP and MOCVD as well as stand-alone atmospheric RTP applications. The UTM™ architecture provides highly modular RTP and MOCVD tool configurations for various single-wafer thermal processes. The UTM™ design comprises a temperature-controlled UHV-grade process chamber as well as an ultraclean gearless wafer rotation assembly for improved temperature uniformity and enhanced built-in reliability. The UTM™ RTP employs bottom/backside wafer heating using a multi-zone axisymmetric illuminator and a reflective multi-zone gas showerhead located above the wafer. Precision RTP control is achieved using a multi-zone controller in conjunction with a multipoint sensor system with real-time multi-zone compensations for wafer emissivity and illuminator light interference effects. The RTP temperature measurement and control techniques fully compensate for any axisymmetric or non-axisymmetric wafer emissivity patterns, eliminating the need for pre-RTP wafer backside conditioning. The UTM™ showerhead provides capabilities for ultraclean multi-zone gas injection and in-situ RF plasma for MOCVD and RTCVD processes. The UTM™ MOCVD module meets the most stringent specifications and tool parameters for various metallization and high-K dielectric deposition applications. This module has been used for deposition of low-resistivity copper films with excellent void-free sub-half-micron gap fill for high-performance multilevel interconnects. The UTM™ RTP and MOCVD modules have been implemented based on design optimizations in a virtual reactor environment.