The increase of test time of embedded DRAM (e-DRAM is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis finction on chip as Built In Self Repair (BISR). BISR is performed at 1661MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7mm2 about 2% of conventional SOC devices. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM functional test time was reduced about 20% less than conventional method at wafer level testing. Moreovel; the results of e-DRAM test and repair analysis using BISR is almost coincident with conventional method.
The computer simulations of the time dependent dielectric breakdown (TDDB) percolation path are performed for ultrathin gate oxides. With our new percolation model, an interesting and new behavior of TDDB distribution was found. Weibull slope decreases monotonously with decreasing oxide thickness, and has a gap at an oxide thickness of approximately the effective defect size. This behavior can be understood well if we consider that an overlap of two neighboring defects becomes necessary to cause a sudden breakdown when oxide thickness exceeds the effective defect size. This phenomenon is very important because Weibull slope has a large effect on device reliability.
An I DDQ test method is proposed in this paper, which is applicable even if supply current measurement is impaired by noise. Wavelet transformation is used for noise elimination in the test method. In this paper, it is shown by some experiments that bridging faults will be detected by using the proposed test method. Since expert knowledge on filter design is not needed in noise elimination of the I DDQ test method, it is expected that the test method will be used in many I DDQ tests.
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