In this work, the concept of reusing a memory location to significantly reduce the overall memory size for storing wide dynamic range (WDR) information in rolling shutter active pixel sensors (APSs) is discussed. At the high light level, WDR is achieved via multiple-resets and real time feedback, allowing a pixel to independently set its integration period as per its ambient light level. Traditionally these WDR bits are stored in a dedicated memory location for every pixel. We propose a new memory architecture which, in principal, is similar to time division multiplexing, such that it achieves memory size reduction by sharing a single memory location among a number of pixels as a function of time. The proposed architecture is ideally suited for rolling shutter APS, where each row is processed sequentially in time. Compared to a commonly used memory design, the proposed architecture becomes increasingly efficient as the pixel count increases, resulting in momentous savings in memory chip area and leakage power consumption. For a pixel array of 128 128, only 14.2% of the commonly used memory bits are required, when using 7 WDR bits per pixel. This requirement reduces to 8.3% of the commonly used memory bits for a pixel array size of 4096 4096, rendering the purposed architecture particularly efficient for larger arrays. The savings in leakage power will track the corresponding savings in memory size and area especially for newer technologies. The purposed concept has been verified in design and simulation for a 128 128 pixel array, fabricated in 180 nm technology.Index Terms-Leakage power reduction, memory size reduction, new memory architecture, wide dynamic range (WDR) CMOS active pixel sensors (APSs).
A highly linear current-controlled delay unit (CCDU) is presented. The proposed design linearly delays an input clock edge against an applied input current. The topology features a directly proportional input/ output relation compared with an inversely proportional one in the traditional current-starved inverter (CSI). The proposed CCDU features a THD of only 0.15% compared with 22.6% in a conventional CSI over the same input dynamic current range of 180 nA. The proposed CCDU is implemented in 65 nm CMOS and consumes only 0.74 μW. An analogue-time-digital ADC is simulated using the proposed CCDU as a front-end block, achieving a resolution (ENOB) of 9.07 bits. Monte Carlo analysis confirms the linearity of the proposed CCDU under mismatch and process variation.Introduction: Low-power analogue-to-digital converters (ADCs) are widely used in wireless sensors and in biomedical fields. For certain distributed sensing applications the speed and resolution of the ADC are less important than the overall power consumption [1]. The ADC proposed in [2] utilises a current mode ring oscillator for conversion. The time mode delta-sigma ADC depicted in [3] utilises a traditional current-starved inverter to tune the oscillator frequency. Most of the time mode and oscillator-based ADCs utilise delay elements (DEs) for analogue-to-time conversion. As such, the design of DEs directly impacts on the performance of such ADCs.Traditional current-starved inverters exhibit an inversely proportional analogue-to-delay conversion relationship [3][4] that is inherently nonlinear. This Letter proposes a new current-controlled delay unit featuring a linear, directly proportional analogue-to-time transfer function. The linearity of the proposed current-controlled delay unit (CCDU) is verified by incorporating its extracted transfer function in a time mode ADC yielding an effective number of bits (ENOB) of 9.07 bits over an input dynamic range of 180 nA.
A distortion-compensated charge transfer amplifier (DCCTA) is proposed to improve the linearity constraints of the differential charge transfer amplifier (DCTA). The proposed DCCTA effectively reduces distortion at its output by source degeneration, cross coupling, and making the drain-to-source voltage of the amplifying transistor independent of the applied input signal. This DCCTA yields an effective number of bits of 9.26 bits, compared with 6.05 bits for the DCTA at 40 MHz while consuming only 13.5 μW from a 1.2-V source. A 1.66-MHz cyclic pipeline analog-to-digital converter employing this DCCTA as a residue amplifier was simulated using 90-nm CMOS process, resulting in a peak resolution of 9.21 bits, without being limited by the thermal noise.Index Terms-Charge transfer amplifier, cyclic pipeline analogto-digital converter (ADC), distortion compensation.
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