In this work, the concept of reusing a memory location to significantly reduce the overall memory size for storing wide dynamic range (WDR) information in rolling shutter active pixel sensors (APSs) is discussed. At the high light level, WDR is achieved via multiple-resets and real time feedback, allowing a pixel to independently set its integration period as per its ambient light level. Traditionally these WDR bits are stored in a dedicated memory location for every pixel. We propose a new memory architecture which, in principal, is similar to time division multiplexing, such that it achieves memory size reduction by sharing a single memory location among a number of pixels as a function of time. The proposed architecture is ideally suited for rolling shutter APS, where each row is processed sequentially in time. Compared to a commonly used memory design, the proposed architecture becomes increasingly efficient as the pixel count increases, resulting in momentous savings in memory chip area and leakage power consumption. For a pixel array of 128 128, only 14.2% of the commonly used memory bits are required, when using 7 WDR bits per pixel. This requirement reduces to 8.3% of the commonly used memory bits for a pixel array size of 4096 4096, rendering the purposed architecture particularly efficient for larger arrays. The savings in leakage power will track the corresponding savings in memory size and area especially for newer technologies. The purposed concept has been verified in design and simulation for a 128 128 pixel array, fabricated in 180 nm technology.Index Terms-Leakage power reduction, memory size reduction, new memory architecture, wide dynamic range (WDR) CMOS active pixel sensors (APSs).
A distortion-compensated charge transfer amplifier (DCCTA) is proposed to improve the linearity constraints of the differential charge transfer amplifier (DCTA). The proposed DCCTA effectively reduces distortion at its output by source degeneration, cross coupling, and making the drain-to-source voltage of the amplifying transistor independent of the applied input signal. This DCCTA yields an effective number of bits of 9.26 bits, compared with 6.05 bits for the DCTA at 40 MHz while consuming only 13.5 μW from a 1.2-V source. A 1.66-MHz cyclic pipeline analog-to-digital converter employing this DCCTA as a residue amplifier was simulated using 90-nm CMOS process, resulting in a peak resolution of 9.21 bits, without being limited by the thermal noise.Index Terms-Charge transfer amplifier, cyclic pipeline analogto-digital converter (ADC), distortion compensation.
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