Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures

Sandhu, Tejinder Singh; El‐Sankary, Kamal

doi:10.1109/tvlsi.2019.2894104

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Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures

Cited by 5 publications

References 8 publications

A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter

A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter

A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM

An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications

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