New Memory Architecture for Rolling Shutter Wide Dynamic Range CMOS Imagers

Abstract

In this work, the concept of reusing a memory location to significantly reduce the overall memory size for storing wide dynamic range (WDR) information in rolling shutter active pixel sensors (APSs) is discussed. At the high light level, WDR is achieved via multiple-resets and real time feedback, allowing a pixel to independently set its integration period as per its ambient light level. Traditionally these WDR bits are stored in a dedicated memory location for every pixel. We propose a new memory architecture which, in principal, is similar to time division multiplexing, such that it achieves memory size reduction by sharing a single memory location among a number of pixels as a function of time. The proposed architecture is ideally suited for rolling shutter APS, where each row is processed sequentially in time. Compared to a commonly used memory design, the proposed architecture becomes increasingly efficient as the pixel count increases, resulting in momentous savings in memory chip area and leakage power consumption. For a pixel array of 128 128, only 14.2% of the commonly used memory bits are required, when using 7 WDR bits per pixel. This requirement reduces to 8.3% of the commonly used memory bits for a pixel array size of 4096 4096, rendering the purposed architecture particularly efficient for larger arrays. The savings in leakage power will track the corresponding savings in memory size and area especially for newer technologies. The purposed concept has been verified in design and simulation for a 128 128 pixel array, fabricated in 180 nm technology.Index Terms-Leakage power reduction, memory size reduction, new memory architecture, wide dynamic range (WDR) CMOS active pixel sensors (APSs).

Analog Encoding Voltage—A Key to Ultra-Wide Dynamic Range and Low Power CMOS Image Sensor

“…Examples of using a digital memory can be found in a large variety of solutions [8] such as (a) multimode sensors that have a linear and a logarithmic response at dark and bright illumination levels, respectively [9]; (b) clipping sensors, in which a well capacity adjustment method is applied [10]; (c) frequency-based sensors, in which the sensor output is converted into a pulse frequency [12]; (d) time-to-first spike (TFS) sensors, in which the image is processed according to the time the pixel was detected as saturated [ 9]; (e) sensors with global control over the integration time, in which the pixel integrates for a set of exposures regardless of its input light intensity [15]; and (f) sensors with autonomous control over the integration time (multiple resets), in which each pixel has control over its own exposure period [16][17][18]. In the aforementioned designs the memories were used to store the possible pixel outputs or the DR extension data.…”