A delta-sigma analog-to-digital converter employs zero-crossing-based integrators to achieve low power operation at 50MHz sampling rate. Switched resistors, used as current sources, provide good dynamic current matching, eliminating the need for common-mode feedback circuits. The effect of the switched resistors on the linearity of the zero-crossing-based integrator is discussed. Also, a unidirectional 2-phase charging scheme is proposed to improve input signal swing and reduce overshoot voltage. Test chip implemented in a 45nm LP Digital CMOS achieves 54.3dB DR, 52.5dB SNR, and 47.7dB SNDR at 0.833MHz input while dissipating 630µW from a 1.1V supply.
A hybrid delta-sigma/pipelined modulator is presented in this paper. The proposed modulator takes advantage of the high resolution and distributed pipelined quantization, and combines it with the noise shaping property of a delta-sigma modulator. As a result, gain, swing, and slew requirements of the integrators are significantly reduced. The modulator also makes use of the latency in the pipelined quantization to enhance noise shaping. These advantages lead to less power dissipation, increased stability, and higher resolution. The prototype chip is implemented in a 0.18 m CMOS process. With an 80 MHz clock, and an oversampling ratio of 8 (5 MHz bandwidth), the measured dynamic range and SNDR of this prototype IC are 79 dB and 75.4 dB.
This paper details the design of an 8-lane bidirectional link for both within-the-box and external communications in 22 nm CMOS technology. A low profile connector with a high density cable assembly ensure a data rate of up to 32 Gb/s per lane while maintaining channel loss below 25 dB. Channel equalization is performed by a combination of a 3-tap feed-forward equalizer (FFE), single-stage continuous-time linear equalizer (CTLE) and a 6-tap decision-feedback equalizer (DFE). Collaborative timing recovery is used to enable lane characterization without degrading jitter performance. Phase error decimation, with a conditional phase detection scheme, is used to reduce the DFE complexity by 50%. Power consumption over a wide range of data rates from 4 to 32 Gb/s is reduced by using regulated CMOS clocking with lane bundling, low swing transmitter with a source-series terminated (SST) driver and a highly reconfigurable receiver with an active inductor CTLE. At a lane data rate of 32 Gb/s, over a 0.5 m cable with 16 dB of loss, a transceiver lane consumes 205 mW from a 1.07 V supply. The power scales down to 26 mW from a 0.72 V supply at 8 Gb/s, when transmitting over a channel with 8 dB loss. The active silicon area per lane is 0.079 mm .Index Terms-Active inductor CTLE, bidirectional link, collaborative CDR, conditional phase detection, decision-feedback equalizer (DFE), phase error decimation, regulated CMOS clocking, source-series terminated (SST) driver.
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