A 630&amp;#x03BC;W zero-crossing-based &amp;#x0394;&amp;#x03A3; ADC using switched-resistor current sources in 45nm CMOS

Musah, Tawfiq; Kwon, Sunwoo; Lakdawala, Hasnain; Soumyanath, K.; Moon, Un-Ku

doi:10.1109/cicc.2009.5280909

Cited by 21 publications

(17 citation statements)

References 8 publications

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“…I(c), they are generated by using inverter-based delay elements and NAND gates. The ZCD is implemented based on the structure presented in [6] for high transition speed.…”

Section: Bmentioning

confidence: 99%

A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators

Yang

Wong

Cai

et al. 2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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A novel fixed-Pulse Shape (PS) clock-jitter insensitive Return-to-Zero (RZ) feedback technique in CT l:A modulators is presented. This technique offers a method to reduce the c1ock jitter effect in feedback DAC. A switched-RC network and a zero-crossing detector are applied to generate jitter insensitive feedback pulse. This technique was verified in a designed 2 nd order CT l:A modulator. A stable 64dB SNDR was obtained with the clock-jitter effect of 2 % of a clock cycle. Simulation results show that using the proposed technique, an SNDR improvement up to 30dB can be achieved comparing with traditional RZ DAC.

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“…I(c), they are generated by using inverter-based delay elements and NAND gates. The ZCD is implemented based on the structure presented in [6] for high transition speed.…”

Section: Bmentioning

confidence: 99%

A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators

Yang

Wong

Cai

et al. 2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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“…1 during the integration phase is given by (14) where for the conventional integrator (15) and for the CP integrator (16) The typical settling behavior of a SC integrator is illustrated in Fig. 4.…”

Section: B Signal Feedforward and Partial Sr-limitationmentioning

confidence: 99%

“…Turning off the OTA for half a clock cycle has also been used to save analog power [12]. Comparator-based switched-capacitor (CBSC) circuits replace the OTAs with more power efficient circuits such as comparators and current sources [13], [14].…”

mentioning

confidence: 99%

A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator

Nilchi

Johns

2013

IEEE Trans. Circuits Syst. I

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Abstract-In this paper a low-power switched-capacitor integrator based on a capacitive charge-pump (CP) is presented, and its practical effects are discussed. The CP integrator is employed as the first stage of a ADC. The 0.13 m CMOS prototype of the CP based ADC achieves the same performance as a conventional ADC while consuming 66% lower OTA power in the front-end integrator. The CP based modulator realizes 87.8 dB SNDR, 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth with 148 W power consumption. The conventional ADC has similar performance but dissipates 241 W. The energy required per conversion-step for the CP based ADC (0.369 pJ/step) is almost 40% lower than that of the conventional ADC (0.607 pJ/step).

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“…Sigma-delta modulators are proven to provide high resolution digital signals [14][15][16][17][18]. In this work we are targeting a low power, low frequency (20 KHz) and high resolution ADC (10 bit).…”

Section: Introductionmentioning

confidence: 99%

A 1.8 V 64.9 uW 54.1 dB SNDR 1<sup>st</sup> order sigma-delta modulator design using clocked comparator Based Switched Capacitor technique

Chakraborty

Sahoo

Rahaman

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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Continued scaling of feature sizes have led to reduction in OpAmp gain thus making it unsuitable for using in a negative feedback system. Comparator Based Switched Capacitor (CBSC) circuits have been proposed as an alternative solution to alleviate this problem. The architecture uses continuous comparators and current sources to detect the virtual ground condition at the input rather than forcing it in the case of an OpAmp. However the architecture consumes static power due to usage of continuous comparators thus making it unsuitable for ultra low power applications. In this work, we use a clocked comparator based switched capacitor circuit technique which mitigates the power concerns by using clocked comparators instead of continuous comparators. The charge transfer phase consists of several cycles and chargingdischarging operation is performed by a number of binary weighted current sources. This work reports the application of this technique in a 1 st order ΣΔ ADC in a 0.18 μm gpdk technology and we achieve 54.1 dB peak SNDR over a 20 KHz bandwidth dissipating 64.9 μW of power from a 1.8 V supply.

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A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS

Cited by 21 publications

References 8 publications

A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators

A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators

A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator

A 1.8 V 64.9 uW 54.1 dB SNDR 1<sup>st</sup> order sigma-delta modulator design using clocked comparator Based Switched Capacitor technique

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