A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator

Abstract:In this paper, a new structure of delta sigma modulator has been proposed in which a second order filter in one stage technique has been taken into the account and a second order noise shaping method and a third order one have been designed by the proposed idea. In the proposed structure an OPAMP has been saved and since in a conventional delta sigma modulator OPAMPs consumes most of the power and takes very large area, the proposed idea causes less power consumption and also the chip area is minimized.

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“…Comparison between the result obtained from the proposed method and ideas presented in [5], [6], [7] and [8] has been presented in table 2. …”

Section: Simulation Results Of the Proposed Second Order Delta Sigma mentioning

confidence: 99%

“…There has been introduced many techniques which provide the same noise transfer function and signal transfer function as the conventional has for the high order noise shaping by mathematical techniques [5][6] [7].…”

Section: Introductionmentioning

confidence: 99%

New Delta Sigma Modulator Structure Using Second Order Filter in One Stage Technique

Dashtbayazi¹,

Sabaghi

Rezaei³

et al. 2014

JEEE

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“…In order to improve the low frequency performance, chopper-stabilization technique has been widely used in the design of operational amplifiers [9,10,11,12,13], SDMs [14,15,16,17,18,19], etc. The basic concept of the chopper-stabilization is that the input signal is in low frequency domain, while the offset of the operational amplifier is modulated up to the chopping frequency which can be easily filtered out.…”

Section: Introductionmentioning

confidence: 99%

A sigma-delta modulator with residual offset suppression

Wu¹,

Zhang²,

Chen³

et al. 2021

IEICE Electron. Express

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This Letter presents a low-residual-offset second-order sigma-delta modulator. By inserting a chopper working at low frequency to the mirrored integrator at the first stage of the modulator, the original residual offset is transferred to a high frequency, which can be removed by the filter. Besides, by applying the second-order fractal sequence as the timing of the new added chopper, the residual offset accumulation problem due to the integration at the second stage can be avoided. To evaluate the effect of residual offset suppression conveniently, a programmable timing is integrated to the design to control the state of the added chopper. The presented modulator is fabricated in a 0.18 um CMOS technology, the core area of which is 0.38 mm 2 . Based on the measurement results, the DC offset of the sigma-delta modulator with the proposed method is reduced by 85.6 μV. The modulator realizes 64.8 dB dynamic range with 1 MHz sampling rate, which consumes 0.96 mW from a 3.3 V supply.

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“…The proposed modulator structure achieves the performance of a conventional modulator while consuming 66% less power in the front‐end charge pump integrator. The modulator can achieve an SNDR of 87.8 dB and a DR of 90 dB over a 10 kHz bandwidth with a power consumption of 148 µW in 0.13 µm CMOS technology [17]. An op‐amp sharing technique was proposed to reduce the power of a delta‐sigma modulator.…”

Section: Introductionmentioning

confidence: 99%

Single low‐gain amplifier compensated hybrid delta‐sigma modulator

Hussain

Choi

2019

IET Circuits, Devices & Systems

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This article presents low-power circuit design techniques to achieve third-order noise shaping by employing multiple stages of passive switched-capacitor gain-boosted integrator and a passive switched-capacitor integrator. First integrator is a passive switched-capacitor for higher linearity. Second integrator is a three-stage passive switched-capacitor gain-boosted integrator to provide passive gain to the loop filter as well as the second DAC feedback. While the third integrator is a two-stage passive switched-capacitor gain-boosted integrator to provide passive gain as well as third DAC feedback for higher stability. Multiple lower stages of passive switched-capacitor gain-boosted integrators employed to enhance the noise shaping order of the modulator and suppress the parasitic effect. The preamplifier is the only active block, while the dynamic comparator used as single-bit quantiser. The complete transistor level with thermal noise simulation can achieve 84 dB of dynamic range (DR), 78.2 dB signal-to-noise-plus-distortion ratio (SNDR), and 78.5 dB signal-to-noise ratio (SNR) for 500 Hz signal bandwidth. It can also achieve signal-to-spurious-free dynamic range (SFDR) of 78.2 dB with estimated power consumption of 220 nW at 1 V supply voltage in SMIC 28 nm CMOS Technology. Finally, it can achieve state-of-the-art Walden Figure-of-Merit (FoM W) of 33 fJ/Conv-Step and Schreier FoM S of 171.2 dB.

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A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator

Cited by 22 publications

References 21 publications

New Delta Sigma Modulator Structure Using Second Order Filter in One Stage Technique

New Delta Sigma Modulator Structure Using Second Order Filter in One Stage Technique

A sigma-delta modulator with residual offset suppression

Single low‐gain amplifier compensated hybrid delta‐sigma modulator

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