An interstage correlated double sampling technique for switched-capacitor gain stages

Sequential interstage correlated double sampling: A switched-capacitor technique for high accuracy systems

“…In Section III, a novel T/H amplifier employing Sequential ICDS technique is proposed, which also triples the effective loop gain in dB and is capable of driving both resistive and capacitive loads. Both architectures provide higher input signal bandwidth compared to the previous sequential architectures [4,6]. The increase in the output thermal noise level in the proposed techniques is negligible.…”

“…This approach causes an increase in the thermal noise level at the output while the approach shown in Fig. 1 doesn't cause an increase in the output thermal noise level [4].…”

“…In the proposed architecture, shown in Fig.2, ICDS [4] and CLS [5] techniques are combined to enhance the effective loop gain compared to the conventional ICDS or CLS. A two stage op-amp is used in this architecture.…”

“…As can be seen in (1), the effective loop gain (≈ Gain Error -1 ) is tripled in dB in the proposed T/H compared to the conventional flip-around T/H amplifier. Compared to 2x-CLS version of the Sequential CLS (SCLS) technique reported in [6] and Cubic ICDS reported in [4], the proposed approach in this work operates in one less clock phase to achieve the same total gain error, which makes this approach more favorable in high speed applications. This is achieved by using C 1n,2n to predict the output during clock phase Φ 1 .…”

“…The rest of this paper is organized as follows: In Section II, a novel T/H amplifier is proposed in which Inter-stage Correlated Double Sampling (ICDS) [4] and Correlated Level Shifting (CLS) [5] techniques are performed sequentially to triple the effective loop gain in dB. In Section III, a novel T/H amplifier employing Sequential ICDS technique is proposed, which also triples the effective loop gain in dB and is capable of driving both resistive and capacitive loads.…”