Plasmonic nanoslits have great potential for single molecule applications. We report a wafer scale process for these structures using process steps compatible with a standard CMOS fab environment. This process allows a large scale fabrication of designed nanoslits with extremely small gap sizes and lengths tuned to exhibit optical resonances. Moreover, adjacent grating nano-antennas were successfully implemented, generating strong and localized electric fields in the nanoslit. These slits have practical applications in surface enhanced Raman spectroscopy-based molecular sensing and plasmonic tweezers.
and comparable with the case where no deep trenches are present.This means that the presence of the deep trench did not introduce A novel scheme for deep trench isolation is presented, which uses additional leakage. The collector-collector isolation is depicted in an airgap as insulator. When incorporated in our 0.13gim SiGe:C Figure 5. In this kind of structures where two n-type regions in a pBiCMOS technology, the peripheral substrate parasitics decrease type substrate are separated by a deep trench, a parasitic conduction with an order of magnitude to a record value of 0.02fF/gm, which channel around the deep trench is present [4]. Due to the absence of significantly improves the device RF performance. a polysilicon plug in the deep trench, there is no gate that can turn on this channel. With a collector-substrate and collector-collector INTRODUCTION breakdown voltage exceeding 100V, the airgap DTI is superior to classical DTI schemes using an oxide/polysilicon filling and is alsoOver the past few years, SiGe:C HBTs have made a tremendous suitable for high voltage applications. The collector-substrate improvement in RF performance. Reduction of device parasitics is capacitance associated with the airgap isolation is strongly reduced key for obtaining even higher speed. Smart device architectures due to a reduction in Ccp. Figure 6 compares Cc for different keyfo obeeconceived to reduce device rincluding irssolation schemes. At reverse bias, a value of 0.02fF/gm is obtained have been cocie ordc eieparasitics, icungraising fothaigpD,whcisaoreofm ntuelerhnfr the extrinsic base regions [1], cutting away unnecessary active device for the airgap DTI, which is an order of magnitude lower than for regions [2] or using double poly architectures with selectively grown classica schemes.base epitaxial layers [3]. Ever since deep trench isolation (DTI) was invented, a strong reduction of the collector-substrate capacitance DEVICE RESULTS(Ccs) was obtained through a reduction of the collector area and the perimeter specific collector-substrate capacitance density (Cc,,p). TheTo demonstrate the impact of the airgap DTI on device latter is usually obtained by partially filling the deep trench with performance, the module is incorporated in our high-speed 0.13gm oxide, which has a low K-value, and the remainder with polysilicon, SiGe:C BiCMOS technology. The architecture for this technology is which acts as a stress-relief buffer. In this work however, we use an based on a low-complexity quasi-self-aligned integration scheme, airgap to isolate devices. The integration scheme is fully compatible which was recently scaled down vertically and laterally towards with standard STI processing and does not require novel materials or high-speed operation [5]. A typical Gummel plot is shown in Figure complex processing steps. Integrating the airgap DTI module in a 7 and shows only a slight impact of the airgap isolation on DC high-speed SiGe:C BiCMOS technology, we will show the isolation device characteristics. Despite the lateral co...
The impact of capacitive coupling effects increases with scaling down the dimensions and towards higher performances. For bipolar technologies, the introduction of deep trench isolation gives a substantial reduction in the collector substrate capacitance. In this paper a method for the formation of airgap deep trenches (with 1μm – depth 6 μm) is presented. The method is fully compatible with standard CMOS Shallow Trench Isolation (STI) and does not require additional masking steps. The approach is based on a partial removal of the poly-Si filling in the trench. Subsequently, inside D-shape oxide spacers are formed narrowing the opening of the trench down. An SF6 plasma is used to convert the nearly completely incorporated poly-Si to volatile SiF4, such that it desorbs through the opening. In the following steps the opening is sealed by depositing SiO2 resulting in the formation of an airgap (patent pending). The normal module for STI formation continues without any adaptation of the process steps. In total four standard additional process steps are needed.The absence of the common oxide/poly filling in the deep trench decreases the peripheral collector substrate capacitance with an order of magnitude to a value of 0.02fF/μm. As a consequence the low power available bandwidth is improved with 90%.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.