2013
DOI: 10.1149/05012.0413ecst
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Wafer Scale Processing of Plasmonic Nanoslit Arrays in 200mm CMOS Fab Environment

Abstract: Plasmonic nanoslits have great potential for single molecule applications. We report a wafer scale process for these structures using process steps compatible with a standard CMOS fab environment. This process allows a large scale fabrication of designed nanoslits with extremely small gap sizes and lengths tuned to exhibit optical resonances. Moreover, adjacent grating nano-antennas were successfully implemented, generating strong and localized electric fields in the nanoslit. These slits have practical applic… Show more

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Cited by 9 publications
(10 citation statements)
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“…In addition, this design of plasmonic nanoslit is compatible with complementary metal–oxide–semiconductor (CMOS) fabrication processes, enabling wafer-level mass-manufacturing (see Supplementary Fig. 1b ) 33 , 34 . To reduce the capacitance of the membrane and prevent potential chemical reactions occurring at the interface, we have deposited a 50 nm SiO 2 layer at the backside (Si side) 35 .…”
Section: Resultsmentioning
confidence: 98%
“…In addition, this design of plasmonic nanoslit is compatible with complementary metal–oxide–semiconductor (CMOS) fabrication processes, enabling wafer-level mass-manufacturing (see Supplementary Fig. 1b ) 33 , 34 . To reduce the capacitance of the membrane and prevent potential chemical reactions occurring at the interface, we have deposited a 50 nm SiO 2 layer at the backside (Si side) 35 .…”
Section: Resultsmentioning
confidence: 98%
“…The processing flow of 200 mm wafer scale silicon nanocavity arrays was previously described. 28 Briefly, nanocavity structures were defined on 8 in. wafers by DUV lithography and anisotropically etched by TMAH.…”
Section: Methodsmentioning
confidence: 99%
“…Deep-UV lithography and standard process steps were used to fabricate rectangular nanoslits in the top Si layer, with open access through the whole wafer, as described in detail before. 28 Figure 1 c shows the additional processing steps. First, a 50 nm layer of PECVD SiN was deposited on the backside to reduce the device capacitance.…”
Section: Solid-state Nanopore Integrated With a Plasmonic Nanoslit Camentioning
confidence: 99%
“…[42] Briefly, the nanocavity structures were defined on 8 in. Experimental Setup: For the experiments in Figure 3, the chip was diced into 3 × 3 mm 2 and rinsed by acetone and Isoproponyl alcohol (IPA).…”
Section: Methodsmentioning
confidence: 99%