A Novel Deep Trench Isolation Featuring Airgaps for a High-Speed 0.13μm SiGe:C BiCMOS Technology

Abstract

and comparable with the case where no deep trenches are present.This means that the presence of the deep trench did not introduce A novel scheme for deep trench isolation is presented, which uses additional leakage. The collector-collector isolation is depicted in an airgap as insulator. When incorporated in our 0.13gim SiGe:C Figure 5. In this kind of structures where two n-type regions in a pBiCMOS technology, the peripheral substrate parasitics decrease type substrate are separated by a deep trench, a parasitic conduction with an order of magnitude to a record value of 0.02fF/gm, which channel around the deep trench is present [4]. Due to the absence of significantly improves the device RF performance. a polysilicon plug in the deep trench, there is no gate that can turn on this channel. With a collector-substrate and collector-collector INTRODUCTION breakdown voltage exceeding 100V, the airgap DTI is superior to classical DTI schemes using an oxide/polysilicon filling and is alsoOver the past few years, SiGe:C HBTs have made a tremendous suitable for high voltage applications. The collector-substrate improvement in RF performance. Reduction of device parasitics is capacitance associated with the airgap isolation is strongly reduced key for obtaining even higher speed. Smart device architectures due to a reduction in Ccp. Figure 6 compares Cc for different keyfo obeeconceived to reduce device rincluding irssolation schemes. At reverse bias, a value of 0.02fF/gm is obtained have been cocie ordc eieparasitics, icungraising fothaigpD,whcisaoreofm ntuelerhnfr the extrinsic base regions [1], cutting away unnecessary active device for the airgap DTI, which is an order of magnitude lower than for regions [2] or using double poly architectures with selectively grown classica schemes.base epitaxial layers [3]. Ever since deep trench isolation (DTI) was invented, a strong reduction of the collector-substrate capacitance DEVICE RESULTS(Ccs) was obtained through a reduction of the collector area and the perimeter specific collector-substrate capacitance density (Cc,,p). TheTo demonstrate the impact of the airgap DTI on device latter is usually obtained by partially filling the deep trench with performance, the module is incorporated in our high-speed 0.13gm oxide, which has a low K-value, and the remainder with polysilicon, SiGe:C BiCMOS technology. The architecture for this technology is which acts as a stress-relief buffer. In this work however, we use an based on a low-complexity quasi-self-aligned integration scheme, airgap to isolate devices. The integration scheme is fully compatible which was recently scaled down vertically and laterally towards with standard STI processing and does not require novel materials or high-speed operation [5]. A typical Gummel plot is shown in Figure complex processing steps. Integrating the airgap DTI module in a 7 and shows only a slight impact of the airgap isolation on DC high-speed SiGe:C BiCMOS technology, we will show the isolation device characteristics. Despite the lateral co...

A 205/275GHz fT/fmax Airgap Isolated 0.13 m BiCMOS Technology featuring on-chip High Quality Passives

“…Compared to the previous DTI module, the oxide/polysilicon trench filling has been replaced by an airgap encapsulated in an oxide plug (figure 1). The integration scheme is fully compatible with standard STI processing and does not require any complex process steps [2]. Since air is the best electrical insulator, the peripheral collector-substrate capacitance C cs,p is further reduced from 0.11fF/µm to a record value of 0.02fF/µm.…”