We designed, prototyped, and evaluated LCD integrated with a gate driver and a source driver using amorphous In-Ga-Zn-Oxide TFTs having bottom-gate bottom-contact structure, thereby obtaining TFTs with superior characteristics.Then, we prototyped the world's first 4-inch QVGA LCD and integrated the gate driver and source driver on the display panel.
We designed, prototyped, and evaluated a liquid crystal panel integrated with a gate driver and a source driver using amorphous In-Ga-Zn-oxide thin film transistors (TFTs). Using bottom-gate bottom-contact (BGBC) thin film transistors, superior characteristics could be obtained. We obtained TFT characteristics with little variation even when the thickness of the gate insulator (GI) film was reduced owing to etching of source/ drain (S/D) wiring, which is a typical process for the BGBC TFT. Moreover, a favorable ON-state current was obtained even when an In-Ga-Znoxide layer was formed over the S/D electrode. Since the upper portion of the In-Ga-Zn-oxide layer is not etched, the BGBC structure is predicted to be effective in thinning the In-Ga-Zn-oxide layer in the future. Upon evaluation, we found that the prototyped liquid crystal panel integrated with the gate and source drivers using the TFTs with improved characteristics had stable drive.
A pass gate (PG) configured with a configuration memory (CM) composed of a c-axis aligned crystalline In-Ga-Zn-O (CAAC-IGZO) FET and a pass transistor composed of an NMOS FET is applied to a multi-context routing switch (MC-RS) of a dynamically reconfigurable programmable logic device (DRPLD) based on multi-context architecture (MC-DRPLD). The proposed PG (OS PG) requires fewer transistors than a conventional PG configured with an SRAM cell served as a CM (SRAM PG). A MC-RS configured with the OS PG (OS MC-RS) has enabled its layout area to be 40% less than that of a MC-RS configured with the SRAM PG (SRAM MC-RS). Further, the delays of the MC-RSs with 2 to 16 contexts have been reduced by 24% to 37%. The MC-DRPLD including the OS MC-RS can switch contexts in one clock (50 nsec) at a clock frequency of 20 MHz, which enables dynamic reconfiguration at high speed.
A multi-context (MC) field-programmable gate array (FPGA) enabling fine-grained power gating (PG) is fabricated by a hybrid process involving a 1.0 µm c-axis aligned crystalline In–Ga–Zn–O (CAAC-IGZO) field-effect transistor (FET), which is one of CAAC oxide-semiconductor (OS) FETs, and a 0.5 µm complementary metal oxide semiconductor (CMOS) FET. The FPGA achieves a 20% layout area reduction in a routing switch and an 82.8% reduction in power required to retain data of configuration memory (CM) cells at 2.5 V driving compared to a static random access memory (SRAM)-based FPGA. A controller for fine-grained PG can be implemented at an area overhead of 7.5% per programmable logic element (PLE) compared to a PLE without PG. For each PLE, the power overhead with fine-grained PG amounts to 2.25 and 2.26 nJ for power-on and power-off, respectively, and break-even time (BET) is 19.4 µs at 2.5 V and 10 MHz driving.
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