A pass gate (PG) configured with a configuration memory (CM) composed of a c-axis aligned crystalline In-Ga-Zn-O (CAAC-IGZO) FET and a pass transistor composed of an NMOS FET is applied to a multi-context routing switch (MC-RS) of a dynamically reconfigurable programmable logic device (DRPLD) based on multi-context architecture (MC-DRPLD). The proposed PG (OS PG) requires fewer transistors than a conventional PG configured with an SRAM cell served as a CM (SRAM PG). A MC-RS configured with the OS PG (OS MC-RS) has enabled its layout area to be 40% less than that of a MC-RS configured with the SRAM PG (SRAM MC-RS). Further, the delays of the MC-RSs with 2 to 16 contexts have been reduced by 24% to 37%. The MC-DRPLD including the OS MC-RS can switch contexts in one clock (50 nsec) at a clock frequency of 20 MHz, which enables dynamic reconfiguration at high speed.
A multi-context (MC) field-programmable gate array (FPGA) enabling fine-grained power gating (PG) is fabricated by a hybrid process involving a 1.0 µm c-axis aligned crystalline In–Ga–Zn–O (CAAC-IGZO) field-effect transistor (FET), which is one of CAAC oxide-semiconductor (OS) FETs, and a 0.5 µm complementary metal oxide semiconductor (CMOS) FET. The FPGA achieves a 20% layout area reduction in a routing switch and an 82.8% reduction in power required to retain data of configuration memory (CM) cells at 2.5 V driving compared to a static random access memory (SRAM)-based FPGA. A controller for fine-grained PG can be implemented at an area overhead of 7.5% per programmable logic element (PLE) compared to a PLE without PG. For each PLE, the power overhead with fine-grained PG amounts to 2.25 and 2.26 nJ for power-on and power-off, respectively, and break-even time (BET) is 19.4 µs at 2.5 V and 10 MHz driving.
An analog multiplier with a hybrid structure where crystalline oxide semiconductor (OS), specifically c-axis-aligned crystalline In-Ga-Zn oxide, based FETs (OS-FETs) are stacked on Si-FETs is fabricated. The analog multiplier demonstrates favorable multiplier characteristics such as high linearity, long data retention, and small device-to-device variation. An analog vector-by-matrix multiplier composed of the analog multiplier and an offset circuit formed of a programmable current source and a programmable current sink with the hybrid structure is proposed. The validity of the proposed analog vector-by-matrix multiplier is verified by employing it in a neural network trained to recognize handwritten digits. According to the circuit simulation results, the analog vector-by-matrix multiplier allows the network to achieve adequately high recognition accuracy, suggesting the suitability of the multiplier for running neural networks.
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