The formation of microscale vertical interconnects enables three-dimensional interconnects for chip stacking applications. These vertical interconnects, or metal filled through silicon vias, are formed by a series of processing steps that include silicon etch, insulation/barrier/seed deposition, electroplated Cu to fill via, wafer grinding and thinning, and back side processing for contacts. Variable diameter size vias residing in the same wafer allow flexibility in integration for many applications. Producing variable size through silicon vias ͑VTSVs͒ on a single wafer is challenging. This article presents details regarding the exposure of VTSV using a unique wafer back side processing technique. Via diameters are in the range of 10-30 m and etch depth varies with via diameter due to the commonly observed reactive ion etch lag. In this approach, the finished wafers are thicker than that produced in a previous project which reduces the risk of wafer breakage during the debonding process.
The formation of vertical interconnects to create three-dimensional (3D) interconnects enables integration of dissimilar electronic material technologies. These vertical interconnects are metal filled blind vias etched in silicon and are formed by a series of processing steps that include: silicon etch; insulation/barrier/seed layer deposition; electroplating of Cu to fill the via; wafer grinding and thinning; and back side processing to form contacts. Deep reactive ion etching (DRIE) is used to etch silicon vias with attention given to process parameters that affect sidewall angle, sidewall roughness, and lateral etch growth at the top of the via. After etching, vias are insulated by depositing 0.5 μm of silicon dioxide by plasma enhanced chemical vapor deposition (PECVD) at 325°C. A barrier film of TaN is reactively sputtered after insulation deposition followed by a Cu sputtered seed film allowing electroplated Cu to fill the blind via. Reverse pulse plating is used to achieve bottom-up filling of the via. Once void-free electroplated vias are prepared, the process wafer is attached to a carrier wafer for silicon back grinding. Vias on the process wafer are “exposed” from the back side of the wafer with a combination of processes that include mechanical grinding, polishing, and reactive ion etching (RIE). Contact pads are then formed by conventional IC processes. Cu posts are used to connect the electronic devices and to address thermal management issues as well. This paper presents materials aspects to consider when fabricating through silicon vias (TSVs). Modeling of the Cu-filled vias to investigate thermal management schemes and Cu posts to investigate mechanical reliability is also presented.
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