Back side exposure of variable size through silicon viasThe formation of a through-silicon via ͑TSV͒ enables three-dimensional ͑3D͒ interconnects for chip-stacking applications that will be especially important for integrating heterogeneous devices. Many processing steps are involved with the major areas including: via formation; deposition of via insulation, barrier, and Cu seed films; Cu electroplating for via-fill; wafer thinning; and backside processing. The via diameter is 4 -8 m, via depth is 15-20 m, and a 20 m pitch is used in this study. Each step will be described in the process flow with the considerations discussed for successful process integration.
A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance-capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense -axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.Index Terms-Copper plating, deep reactive ion etching (DRIE), reactive ion etching (RIE), through-silicon vias (TSV), Vertically Integrated Sensor Arrays (VISA), via processing, -axis interconnects.
The etching of anisotropic blind vias in silicon with diameters of 5-10 m and an aspect ratio ϳ2-4 with controlled sidewall inclination is reported. The motivation for this work is the creation of a vertical, or three dimensional interconnect. Via formation by reactive ion etch ͑RIE͒ processing is the focus of this project. Arrays of vias have been etched in 125 mm diam silicon ͑100͒ wafers using a photoresist mask. A parallel plate RIE system with a SF 6 /O 2 gas mixture is used. The effects of O 2 / ͑SF 6 +O 2 ͒ gas flow ratio, electrode bias, and chamber pressure on etch rate and feature profile have been studied. Visualization of the via profiles using scanning electron microscopy is used to identify the key parameters that control the sidewall slope. This slope is important for the subsequent deposition of via lining materials before filling with Cu. Our results indicate that the O 2 / ͑SF 6 +O 2 ͒ ratio is a key parameter in determining the sidewall slope, however the electrode bias and chamber pressure are critical in determining the physical and chemical process balance that determine the anisotropy of the etch process.
The effect of process parameters on blind via formation for vertical interconnects using an STS deep reactive ion etch tool is reported. A modified Bosch process is used to create vias ͑20 and 25 m in diameter͒ with varying depths and sidewall angles on 125 mm diameter silicon wafers using a photoresist mask. The effect of changing the flow rates of SF 6 and C 4 F 8 gases, the automatic pressure control angle, and coil and platen powers on via profile and sidewall morphology is studied. The effect of chamber cleaning and conditioning on controlling the diameter growth at the top surface of the via is also reported. The various via profiles are examined using an environmental scanning electron microscope and by observing via cross sections. Each parameter plays a critical role in obtaining a specified via profile. A sloped via sidewall is required for our application of fabricating vertical interconnects. After etching, vias are insulated by depositing 2 m of silicon dioxide by plasma enhanced chemical vapor deposition at 250°C. A barrier film of TaN is reactively sputtered after insulation deposition followed by a Cu sputtered seed film allowing electroplated Cu to fill the via. The sloped via sidewall is required due to the weak step coverage obtained by sputter deposition.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.