In the current investigation, an innovative time-domain damage index is introduced for the first time which is based on local statistical features of the waveform. This damage index is called the ‘normalized correlation moment’ (NCM) and is composed of the nth moment of the cross-correlation of the baseline and comparison waves. The performance of this novel damage index is compared for some synthetic signals with that of an existing damage index based on the Pearson correlation coefficient (signal difference coefficient, SDC). The proposed damage index is shown to have significant advantages over the SDC, including sensitivity to the attenuation of the signal and lower sensitivity to the signal’s noise level. Numerical simulations using Abaqus finite element (FE) software show that this novel damage index is not only capable of detecting the delamination type of damage, but also exhibits a good ability in the assessment of this type of damage in laminated composite structures. The NCM damage index is also validated using experimental data for identification of delamination in composites.

Time-multiplexed etching, the Bosch process, is a technique consisting of alternating etch and deposition cycles to produce high aspect-ratio etched features. The Bosch process uses SF 6 and C 4 F 8 as etch and polymer deposition gases, respectively. In these experiments, polymer thickness is controlled by both C 4 F 8 gas flow rates and by deposition cycle time. The authors show that polymer thickness can be used to control wall angle and curvature at the base of feature walls. Wall angle is found to be independent of trench width under thin-polymer deposition conditions. Experimental results are compared to results obtained by other researchers using the more conventional simultaneous etch/deposition technique.

Back side exposure of variable size through silicon viasThe formation of a through-silicon via ͑TSV͒ enables three-dimensional ͑3D͒ interconnects for chip-stacking applications that will be especially important for integrating heterogeneous devices. Many processing steps are involved with the major areas including: via formation; deposition of via insulation, barrier, and Cu seed films; Cu electroplating for via-fill; wafer thinning; and backside processing. The via diameter is 4 -8 m, via depth is 15-20 m, and a 20 m pitch is used in this study. Each step will be described in the process flow with the considerations discussed for successful process integration.

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance-capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense -axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.Index Terms-Copper plating, deep reactive ion etching (DRIE), reactive ion etching (RIE), through-silicon vias (TSV), Vertically Integrated Sensor Arrays (VISA), via processing, -axis interconnects.

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