Roughness effect on uniformity and reliability of sequential lateral solidified low-temperature polycrystalline silicon thin-film transistors were studied by comparison of transistors made on a thin-film substrate with and without planarization process. The two-step planarization process, including the wet etching of the precursor and a fine-tuned laser annealing procedure, can reduce the average roughness level to less than 1.4 nm. The results show that transistors without protrusion around the grain boundaries have higher threshold voltage uniformity, smaller subthreshold swing, larger breakdown voltage, and better reliability under high field stress than those made without planarization process.Polycrystalline silicon ͑poly-Si͒ thin-film transistors ͑TFTs͒ are attractive as the active devices in the driver circuits of active-matrix liquid-crystal display ͑AM-LCD͒ 1 and active-matrix organic lightemitting diode display ͑AM-OLED͒. 2 Recently, the performance gap between poly-Si TFTs and single-crystalline silicon devices has become smaller as a result of the advancement in poly-Si crystallization techniques. To meet system on panel ͑SOP͒ applications, the poly-Si film quality must be optimized for performance, throughput, and uniformity. Excimer-laser crystallization ͑ELC͒ is the most promising method of fabricating high quality poly-Si film on glass because of its ability to melt Si films without thermal damage to the glass substrate.High surface roughness as a result of protrusions at the grain boundaries is an inherited problem of laser crystallized poly-Si films. 3 During crystallization, silicon transforms from liquid phase to solid phase. The density variation caused by phase transformation generates liquid silicon accumulation in the last solidified area, grain boundaries, thus protrusions are formed. Poor device performance, uniformity, and reliability resulting from poly-Si surface roughness worsen when scaling of channel length and gate insulator in TFT is required in advance applications. 4-7 In addition, chemical mechanical polishing ͑CMP͒ was used on the laser-crystallized silicon film to reduce interface roughness. 8-10 Unfortunately, the glass size is 730 ϫ 920 mm in generation 4.5 glass now, and the process of CMP therefore is not suitable for flat panel displays.In this paper, the sequential lateral solidification ͑SLS͒ laser annealing process was utilized to produce uniform, large-grain microstructure in Si thin films. Low-temperature polycrystalline silicon ͑LTPS͒-TFTs with or without surface planarization process were fabricated in the Generation 2 production line ͑glass size: 370 ϫ 470 mm͒, respectively. The roughness effect of SLS poly-Si films on the electrical characteristics of the sample devices is studied. In addition, the uniformity and reliability of SLS LTPS TFTs with planarization process is investigated.
ExperimentalThe poly-Si TFT samples were fabricated on glass substrate with and without planarization process. The process sequence for sample fabrication was as follows. Buffer S...
Characteristics and stress-induced degradation of laser-activated low temperature polycrystalline silicon thin-film transistors J. Appl. Phys. 93, 1926(2003; 10.1063/1.1535732Large-grain polycrystalline silicon films with low intragranular defect density by low-temperature solid-phase crystallization without underlying oxide
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