We study the problem of performing buffer insertion in the context of a given layout. In a practical situation, there are restrictions on where buffers may be inserted; for instance, it may be possible to route wires over a preplaced macro cell, but may not be possible to insert buffers in that region. As a result, it is desirable to perform route planning and buffer insertion simultaneously. Furthermore it is necessary that such an algorithm be aware of the trade-off between cost (e.g., total capacitance) and delay. In this context we propose the delay reduction to cost ratio (DRCR) problem and present a fast algorithm for the same. Solutions identified by the algorithm are characterized with respect to the overall cost versus performance trade-off curve. Computational experiments demonstrate the viability of the approach.
This paper studies a natural formulation of the timing driven maze routing problem.A multi-graph model appropriate for global routing applications is adopted; the model naturally captures blockages, limited routing and wire-sizing resources (and perhaps spacing resources). Each edge in the multi-graph is annotated with resistance and capacitance values associated with the particular wiring segment. The timing driven maze routing problem is then to find paths which exhibit low RC delay or achieve a tradeoff between RC delay and total capacitance. An easy-to-implement labeling algorithm is presented to solve the problem along with effective speedup enhancements to the basic algorithm which yield up to 300X speedup. It is suggested that such an algorithm will become a fundamental tool in an arsenal of interconnect optimization techniques. The tractability of the approach is supported via computational experiments.
SUMMARYTo deal with failures as simply as possible, we propose a new foundation for the core (untyped) C ++ , which is based on a new logic called task logic or imperative logic. We then introduce a sequentialdisjunctive statement of the form S : R. This statement has the following semantics: execute S and R sequentially. It is considered a success if at least one of S , R is a success. This statement is useful for dealing with inessential errors without explicitly catching them.
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