Timing driven maze routing

Hur, Sung-Woo; Jagannathan, Ashok; Lillis, John

doi:10.1145/299996.300079

Cited by 14 publications

(13 citation statements)

References 11 publications

(4 reference statements)

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“…Another work in the area of crosstalk reduction has been done in [2], [6] where the parasitic coupling capacitance occurs in the cost function formulation of the routing methodology and during layer track assignment respectively. The authors in [7], [8], [9] have developed various performance driven routing strategies using a simple Elmore (RC) delay model for the interconnects. Cong et al [10], have used higher order RLC model in their MINOTAUR global router but they have not considered interwire inductive and capacitive coupling.…”

Section: Related Workmentioning

confidence: 99%

Parasitic aware routing methodology based on higher order RLCK moment metrics

Bhaduri

Vemuri

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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In the multi-GHz frequency domain, inductive and capacitive parasitics of interconnects can cause significant 'ringing' or overdamping, which may lead to false switching or increased delay. Routing techniques which rely on wire length reduction or coupling capacitance minimization are unable to obtain the best routing solution. In this paper, the inductive and capacitive interactions of the wires are introduced through a 'moment' based cost function. This higher order RLCK moment metric guides the routing process of long wires, ensuring that the chosen solution has the best trade-off between ringing and delay under a monotone signal response. Another significant departure from existing routing methodologies is to account for the signal direction in the nets which may increase or decrease the effective inductive and capacitive parasitics.

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Section: Related Workmentioning

confidence: 99%

Parasitic aware routing methodology based on higher order RLCK moment metrics

Bhaduri

Vemuri

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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“…8). We let the branching point solutions form the initial wavefront (note that the wavefront entries are triples [ , , ] not scalars as in traditional shortest paths) and expand in a manner similar to [7] and [15].…”

Section: Generalized Dijkstra's Algorithmmentioning

confidence: 99%

“…We apply case 3 at the root since some solution in the left subtree dominates (has smaller cost and load and better slack). Suppose instead the query is (10,7); in this case, we traverse the tree all the way to the vertex (12,8) and, finally, a NULL subtree to conclude that it is nondominated. If the query is (10,15), we apply case 2 at the root and declare it nondominated.…”

Section: E Dominance Property and Pruningmentioning

confidence: 99%

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Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages

Hrkić

Lillis

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We give an overview of a buffer tree synthesis package which pays particular attention to the following issues: routing and buffer blockages, minimization of interconnect and buffer costs, congestion, exploitation of temporal locality among the sinks, and addressing sink polarity requirements. Experimental results demonstrate the effectiveness of the tool in comparison with previously proposed techniques.

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“…A technique for timing driven maze routing has been proposed recently in [43,44] Both maze routing and line probe methods are designed for connecting two pin nets. However, in practice, nets with more than two pins are often encountered in the routing problem.…”

Section: Maze Routingmentioning

confidence: 99%

A survey on multi-net global routing for integrated circuits

Sapatnekar

2001

Integration

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This paper presents a comprehensive survey on global routing research over about the last two decades, with an emphasis on the problems of simultaneously routing multiple nets in VLSI circuits under various design styles. The survey begins with a coverage of traditional approaches such as sequential routing and rip-up-and-reroute, and then discusses multicommodity flow based methods, which have attracted a good deal of attention recently. The family of hierarchical routing techniques and several of its variants are then overviewed, in addition to other techniques such as move-based heuristics and iterative deletion. While many traditional techniques focus on the conventional objective of managing congestion, newer objectives have come into play with the advances in VLSI technology. Specifically, the focus of global routing has shifted so that it is important to augment the congestion objective with metrics for timing and crosstalk. In the later part of this paper, we summarize the recent progress in these directions. Finally, the survey concludes with a summary of possible future research directions.

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Timing driven maze routing

Cited by 14 publications

References 11 publications

Parasitic aware routing methodology based on higher order RLCK moment metrics

Parasitic aware routing methodology based on higher order RLCK moment metrics

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages

A survey on multi-net global routing for integrated circuits

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