A survey on multi-net global routing for integrated circuits

Abstract

This paper presents a comprehensive survey on global routing research over about the last two decades, with an emphasis on the problems of simultaneously routing multiple nets in VLSI circuits under various design styles. The survey begins with a coverage of traditional approaches such as sequential routing and rip-up-and-reroute, and then discusses multicommodity flow based methods, which have attracted a good deal of attention recently. The family of hierarchical routing techniques and several of its variants are then overviewed, in addition to other techniques such as move-based heuristics and iterative deletion. While many traditional techniques focus on the conventional objective of managing congestion, newer objectives have come into play with the advances in VLSI technology. Specifically, the focus of global routing has shifted so that it is important to augment the congestion objective with metrics for timing and crosstalk. In the later part of this paper, we summarize the recent progress in these directions. Finally, the survey concludes with a summary of possible future research directions.

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

“…There are two main strategies for routing according to the approach used to create the routes for each net: sequential (one net at a time) and concurrent (all nets simultaneously) [16].…”

Efficient Rerouting Algorithms for Congestion Mitigation

“…In the past decades, researchers have relentlessly strived to improve the performance of global routing algorithms (see e.g., [1], [2], [3], and references therein). To handle the *Corresponding author M. A. R. Chaudhry, email: masadch@tamu.edu.…”

Minimum Steiner Tree Construction*

“…The Iterated 1-Steiner algorithmic template also generalizes to produce Steiner arborescences, i.e., shortest-paths trees with minimum wirelength, which are known to yield high-performance critical net routings [45]. The Iterated Dominance (IDOM) graph arborescence heuristic of [2] recapitulates the Iterated 1-Steiner strategy, by greedily iterating over a given spanning arborescence construction.…”

“…In modern deep-submicron VLSI layout other criteria often dominate the routing objectives, such as path lengths, skew, density, inductance, manufacturability, electromigration, reliability, noise, power, non-Hanan topologies, signal integrity, three-dimensionality, alternate models, and various combinations and tradeoffs of these [3,5,12,27,44,45,46,50,52,57,67,70,86].…”