Efficient Rerouting Algorithms for Congestion Mitigation

Chaudhry, Mohammad Asad Rehman; Asad, Zakia; Sprintson, Alex; Hu, Jiang

doi:10.1109/isvlsi.2009.38

Cited by 3 publications

(1 citation statement)

References 31 publications

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“…A preliminary version of this paper appeared in the proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) [27]. This work was supported in part by NSF grant CNS-0954153.…”

Section: Acknowledgmentmentioning

confidence: 99%

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

et al. 2011

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In the advent of smaller devices, a significant increase in the density of on-chip components has raised congestion and overflow as critical issues in VLSI physical design automation. In this paper, we present novel techniques for reducing congestion and minimizing overflows. Our methods are based on ripping up nets that go through the congested areas and replacing them with congestion-aware topologies. Our contributions can be summarized as follows. First, we present several efficient algorithms for finding congestion-aware Steiner trees that is, trees that avoid congested areas of the chip. Next, we show that the novel technique of network coding can lead to further improvements in routability, reduction of congestion, and overflow avoidance. Finally, we present an algorithm for identifying efficient congestion-aware network coding topologies. We evaluate the performance of the proposed algorithms through extensive simulations.

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Section: Acknowledgmentmentioning

confidence: 99%

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

et al. 2011

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Max-Flow Min-Cost Routing in a Future-Internet with Improved QoS Guarantees

Szymański

2013

IEEE Trans. Commun.

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Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT

Kundu

Roy

Mukherjee

2022

J CIRCUIT SYST COMP

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In this paper, Pseudo-Boolean Satisfiability (PB-SAT)-based congestion reduction and overflow minimization techniques are introduced for constructing congestion-aware rectilinear Steiner trees for global routing in IC design. Since congestion in different routing channels is a big issue in routing nets, various congestion minimization approaches have been proposed by many researchers. However, the increasing complexity of integrated circuits and the reduction of their size make the congestion problem more complicated. The proposed method can produce a congestion-free routing solution by generating a suitable rectilinear Steiner tree for circuit nets. To reduce the complexity of the problem, the nets are solved individually using a Minimum Bounding Box (MBB)-based heuristic technique. The algorithm is validated by utilizing the well-known ISPD 98 global routing benchmarks. Experimental results prove that the methodology is capable of routing most of the nets within the given routing capacity satisfying all the routing parameters. The results also show that the algorithm can produce congestion-aware Steiner trees efficiently within a nominal time-bound.

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Efficient Rerouting Algorithms for Congestion Mitigation

Cited by 3 publications

References 31 publications

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

Max-Flow Min-Cost Routing in a Future-Internet with Improved QoS Guarantees

Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT

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