We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure f r om previous approaches in that we derive an explicit area/delay tradeo curve. We achieve this goal by limiting the solution space to the set of topologies induced b y a p ermutation on the sinks of the net. This constraint allows ecient identication of optimal solutions while still providing a rich solution space. We also incorporate simultaneous wire sizing. Our technique consistently p r o duces topologies equalling the performance o f previous approaches with substantially less area overhead.

Abstract. We describe fully polynomial time approximation schemes for generalized multicommodity flow problems arising in VLSI applications such as Global Routing via Buffer Blocks (GRBB). We extend Fleischer's improvement [7] of Garg and Könemann [8] fully polynomial time approximation scheme for edge capacitated multicommodity flows to multiterminal multicommodity flows in graphs with capacities on vertices and subsets of vertices. In addition, our problem formulations observe upper bounds and parity constraints on the number of vertices on any source-to-sink path. Unlike previous works on the GRBB problem [5,17], our algorithms can take into account (i) multiterminal nets, (ii) simultaneous buffered routing and compaction, and (iii) buffer libraries. Our method outperforms existing algorithms for the problem and has been validated on top-level layouts extracted from a recent high-end microprocessor design.

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