Simultaneous routing and buffer insertion for high performance interconnect

Lillis, John; Cheng, Chung‐Kuan; Lin, Tingting

doi:10.1109/glsv.1996.497611

Cited by 54 publications

(32 citation statements)

References 9 publications

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“…Also more results are listed in table (11) for an interconnect wire of length 20000µm. As can be seen distances between buffers have become equal to each other, in which the errors are lower than 0.28%.…”

Section: Experimental Results Of Delay Minimization Using Pso Algorithmmentioning

confidence: 99%

“…In these studies, the delay minimization problem of on-chip interconnect wire is considered by simultaneous buffer insertion/sizing, and wire sizing. In fact, by manipulating the wire width, for example, the trade-off between capacitance and resistance can be balanced, and consequently the delay can be minimized [11]. On the other hand, correct buffer insertion area able to minimize signal delay by repowering the signal using amplifiers or buffers [12].…”

Section: Introductionmentioning

confidence: 99%

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Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

Karimi¹,

Ahmadi²

2014

Appl. Math. Inf. Sci.

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This paper considers the problem of interconnect wire delay in digital integrated circuits. The correct wire sizing and buffer insertion/sizing can reduce the interconnect delay. The interconnect wire is divided into segments and to optionally buffers are inserted between two adjacent segments. But it is important to select appropriate values for the size of buffers as well as the lengths and widths of segments to minimize the delay. Since the delay is a multi-dimensional function, its optimizing process is complex and time-consuming. In this paper we introduce an improved particle swarm optimization for delay minimization. The aim is to reduce the interconnect wire delay. This work is performed in 3 case studies. Sizing a chain of buffers without considering the wire delay is done in case study 1. Wire sizing alone and buffer insertion/sizing with wire sizing are dealt in case study 2 and case study 3 respectively. In these case studies, the our improved PSO results are matched with theoretical results while the proposed technique is very fast and more accurate than standard techniques.

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Section: Experimental Results Of Delay Minimization Using Pso Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

Karimi¹,

Ahmadi²

2014

Appl. Math. Inf. Sci.

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“…If one does not accept the restriction that the Steiner tree is fixed before buffer insertion is performed, then a suite of other heuristics emerge [8], [12]- [14], [16]. These heuristics all in some way exploit the dynamic programming paradigm, but in a manner that allows multiple tree topologies to be considered.…”

Section: Introductionmentioning

confidence: 99%

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Alpert

Chu

Gandham

et al. 2002

Proceedings of the 2002 International Symposium on Physical Design

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Abstract-To achieve timing closure in a placed design, buffer insertion and driver sizing are two of the most effective transforms that can be applied. Since the driver-sizing solution and the buffer-insertion solution affect each other, suboptimal solutions may result if these techniques are applied sequentially instead of simultaneously. We show how to simply extend van Ginneken's buffer-insertion algorithm to simultaneously incorporate driver sizing and introduce the idea of a delay penalty to encapsulate the effect of driver sizing on the previous stage. The delay penalty can be precomputed efficiently via dynamic programming. Experimental results show that using driver sizing with a delay-penalty function obtains designs with superior timing and area characteristics.Index Terms-Buffer insertion, driver sizing, interconnection optimization, performance optimization.

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“…[1] developed a power-optimal buffer insertion algorithm to meet the delay specification. The buffered tree construction problem was studied without buffer stations (BS) or blockages in [2,3], and with BS blockage avoidance in [4,5,6,7]. Power was not considered explicitly in [2]- [7].…”

Section: Introductionmentioning

confidence: 99%

Power optimal dual-Vdd buffered tree considering buffer stations and blockages

Tam¹,

He²

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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This paper presents the first in-depth study on applying dual V dd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constraint. To tackle the problem of dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices, we develop a sampling-based sub-solutions (i.e. options) propagation method and a balanced search tree-based data structure for option pruning. We obtain 17x speedup with little loss of optimality compared to the exact option propagation. Moreover, compared to buffer insertion with single V dd buffers, dual-V dd buffers reduce power by 23% at the minimum delay specification. In addition, compared to the delay-optimal tree using single V dd buffers, our power-optimal buffered tree reduces power by 7% and 18% at the minimum delay specification when single V dd and dual V dd buffers are used respectively.

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Simultaneous routing and buffer insertion for high performance interconnect

Cited by 54 publications

References 9 publications

Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Power optimal dual-Vdd buffered tree considering buffer stations and blockages

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