A fast algorithm for context-aware buffer insertion

Abstract

We study the problem of performing buffer insertion in the context of a given layout. In a practical situation, there are restrictions on where buffers may be inserted; for instance, it may be possible to route wires over a preplaced macro cell, but may not be possible to insert buffers in that region. As a result, it is desirable to perform route planning and buffer insertion simultaneously. Furthermore it is necessary that such an algorithm be aware of the trade-off between cost (e.g., total capacitance) and delay. In this context we propose the delay reduction to cost ratio (DRCR) problem and present a fast algorithm for the same. Solutions identified by the algorithm are characterized with respect to the overall cost versus performance trade-off curve. Computational experiments demonstrate the viability of the approach.

Buffer insertion with adaptive blockage avoidance

“…This algorithm is based on a dynamic programming framework similar to van Ginneken's algorithm, but the entire grid graph is searched instead of a fixed topology. The authors of [11] and [12] also considered blockage avoidance with buffer insertion using graph based approaches for two-pin nets. It is not clear how to extend these methods [21,11,12] directly to multi-pin nets.…”

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages

“…Many of the practical buffer insertion techniques in use today can be traced to the seminal work of van Ginneken [13] which proposed a dynamic programming algorithm for inserting buffers into a given rooted topology. In addition, buffer insertion techniques for two-pin nets have received some attention [8], [15]. In the area of routing topology construction, there are several works of particular relevance to this paper.…”

Tradeoff routing resource, runtime and quality in buffered routing

“…If D is less than D r , then we increase the value of λ, apply the graph-based algorithm with the new value λ and repeat the process until we find a satisfactory solution. We use binary search to find the appropriate λ as in [4] …”

“…the signal delay and routing cost respectively, and λ is the factor to balance the two items; second, minimizing routing cost subject to a delay constraint; third, minimizing delay while cost does not exceed some given budget; fourth, given a required delay constraint D r , maximizing the delay reduction to cost ratio (DRCR), D r D C . Jagannathan et al [4] studied the buffer insertion problem to maximize the DRCR for 2-pin nets, which limits the application since in practice many nets have more than 2 pins. It is suggested in [4] that the DRCR is a natural composite objective function capturing the tradeoff between cost and delay.…”

“…Jagannathan et al [4] studied the buffer insertion problem to maximize the DRCR for 2-pin nets, which limits the application since in practice many nets have more than 2 pins. It is suggested in [4] that the DRCR is a natural composite objective function capturing the tradeoff between cost and delay. However, the primary problem to tradeoff cost and delay is to minimize the linear combination of delay and cost, D ¡ λC.…”