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By manipulating the charge profile through the inverted sidewall patterning on the channel, stable 2-bit operation in silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm gate length can be achieved. The fabricated memory cell has about 30-nm twin Oxide-Nitride-Oxide-Silicon physically separated by the inverted sidewall patterning method under the same control gate based on damascene gate process. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better endurance, retention, and erase speed than SSM can be obtained in the short (sub-100-nm) gate length devices.

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The electrical properties of a split-gate-type flash cell are investigated and optimized by junction engineering to obtain a high reliability. Phosphorus implantation is conducted to form a cell source junction, and the following three different anneal conditions change voltage coupling ratio between the source and the floating gate. As the ratio increases, it is observed that program characteristic is improved and endurance property is degraded, which matches well with simulation result. Therefore, cells in the pure N2 group are considered to be optimized cells. Optimized cells guarantee 105 cycle endurance, and show excellent program disturbance and bake retention properties.