Twin SONOS Memory With 30-nm Storage Nodes Under a Merged Gate Fabricated With Inverted Sidewall and Damascene Process

Abstract

By manipulating the charge profile through the inverted sidewall patterning on the channel, stable 2-bit operation in silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm gate length can be achieved. The fabricated memory cell has about 30-nm twin Oxide-Nitride-Oxide-Silicon physically separated by the inverted sidewall patterning method under the same control gate based on damascene gate process. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better endurance, retention, and erase speed than SSM can be obtained in the short (sub-100-nm) gate length devices.

Simulation of Nanoscale Two-Bit Not-And-type Silicon–Oxide–Nitride–Oxide–Silicon Nonvolatile Memory Devices with a Separated Double-Gate Fin Field Effect Transistor Structure Containing Different Tunneling Oxide Thicknesses

“…[6][7][8] In particular, NANDtype NVMs with nanoscale gates have attracted much interest because of the fabrication of NVM devices with ultrahigh-density and low-power elements. 9,10) However, the electrical properties of scaled-down conventional NVM devices have serious problems due to the short channel effect (SCE), tunneling effect or leakage current at the oxide/ silicon heterointerface, and the coupling capacitance between cells. 11) Fin field effect transistor (FinFET) structures have emerged as excellent candidates for applications in next-generation NVM devices because of their good SCE immunity, high read current, and high punch-through margin.…”

Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure

“…The saddle MOSFET has advantages such as excellent short-channel effect immunity, less DIBL, reasonable V th . SONOS type flash memory cell for multi-bit operation uses nitride layer to localize charge trapping [11], [12].…”

A Novel Gate-Assisted Reverse-Read Scheme to Control Bit Coupling and Read Disturb for Multibit/Cell Operation in Deeply Scaled Split-Gate SONOS Flash EEPROM Cells

“…The charges have to be kept physically isolated on the source (S) and drain (D) sides, memory window reduction due to bit coupling [6] during reverse read needs to be kept under control, and read V D must be kept low enough (note that reduced read V D increases bit coupling) to prevent read disturb for scaled cells. Specially designed split-gate cells where the ONO stack was patterned using either a sidewall spacer combined with a damascene process [7] or dual patterning of deposited polysilicon [8] were used for better physical isolation of charges compared with simple stack-gate cells [3]. While spatial separation of 2 bit is achievable, bit coupling still remains a concern in [7] that electrostatically resembles a stacked gate cell with isolated charge storage nodes, while in [8], independent control gate (CG) access is needed to make the channel conductive.…”

“…Specially designed split-gate cells where the ONO stack was patterned using either a sidewall spacer combined with a damascene process [7] or dual patterning of deposited polysilicon [8] were used for better physical isolation of charges compared with simple stack-gate cells [3]. While spatial separation of 2 bit is achievable, bit coupling still remains a concern in [7] that electrostatically resembles a stacked gate cell with isolated charge storage nodes, while in [8], independent control gate (CG) access is needed to make the channel conductive. Recently [9], channel-engineered SONOS cells having a combination of compensation and halo implants were used to optimize bit coupling and read disturb.…”