The structure of novel 2-bit/cell silicon-oxide-nitride-oxide-silicon (SONOS) flash memory device was proposed and characterized for sub-50 nm non-volatile memory (NVM) technology. A proposed memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region. It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the V th margin for 2-bit/cell operation by $2:5 times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the V th margin more than $1:5 V.
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