In this paper, we investigate a new generalized selection combining (GSC) technique and an adaptive rake combining scheme to save the power consumption of mobile rake receivers for wideband CDMA systems. The new GSC technique called minimum selection GSC (MS-GSC) selects a minimum number of rake fingers, while maintaining the combined SNR larger than a given threshold. The proposed adaptive rake combining scheme dynamically adjusts the threshold value to maintain the desired BER. Therefore, our rake combining scheme can be integrated into any GSC, which select fingers based on a given threshold value. The proposed MS-GSC shows a low standard deviation in bit error statistics and is advantageous in practical implementation. Our experiments indicate that the proposed adaptive combining scheme reduces the power consumption of a mobile rake receiver up to 67.8 % by turning off unselected rake fingers.

As state-of-the-art mobile devices are demanded for high performance and attractive designs, system-on-chips have been integrated with many functional blocks into a single chip to reduce the chip size, cost, and power consumption. In this paper, to reduce power consumption of heterogeneous processor, a power management algorithm is proposed with a time-based power control architecture which autonomously performs voltage/clock scaling operations without the intervention of the processors. The proposed algorithm has adaptively adjusted time-threshold levels for voltage/clock control to minimize the power consumption and work in severe time-constraints for real-time processing. The real-time adjustment makes robust performance of the power consumption guarantee regardless of patterns of data traffic and diverse application programs. To show performance of the proposed, they are adopted to an application processor integrated with a communication processor for smartphones. Via electronic system-level simulation, it is shown that the proposed algorithm reduces the power consumption by approximately 40%.

This paper presents dynamic power saving schemes for low power operation in the modem system shared memory architecture of mobile system-on-a-chip (SOC). Different power modes are considered to obtain the minimum power consumption in a modem operation. An electronic system level (ESL) virtual platform is implemented to verify the proposed scheme with real traffic data extracted from the actual phone. Experimental results show that the proposed method reduces the power consumption by 42% and 15% in 2G and 3G respectively.

An architecture is proposed to design a single chip with an application processor (AP) and a modem processor (MP). As an aggressive challenge, the MP's dedicated memory is removed to share the main memory with the AP. In addition, an autonomous power management (APM) is presented to reduce the power consumption of time-constrained tasks such as wireless communication. The APM is designed without the intervention of the microprocessors, to deal with the random and sparse data pattern of voice communication. For the architectural exploration, an electronic system-level simulation is performed for verifying the performance and power consumption. Through the simulation results, the proposed architecture exhibits small size, good performance and energy consumption.