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A proximity estimation algorithm is proposed to measure distances between a transceiver and a receiver for location-based services in indoor environments. To improve the measurement accuracy, proximity is estimated using the propagation delay caused by the roundtrip travel of the signal. Moreover, to reduce power consumption, frequency downconversion with a mixer is adopted to use frequencies below the gigahertz range. Being a low-power design, the proposed architecture is suitable for mobile devices such as wearable and internet-of-things products. In addition, the implementation of this algorithm on Wi-Fi-equipped devices does not need development of special schematics, since it is based on the IEEE 802.11 standard, it could be made with usual Wi-Fi quadrature amplitude modulation (QAM)-modulators. The accuracy enhancement of the proposed estimation was verified in comparison with the conventional algorithms by means of simulation. Introduction:A key technology for internet-of-things and locationbased service (LBS) is the indoor positioning system. Present indoor positioning systems consist of an inertial navigation system with microelectromechanical system sensors, fingerprinting methods based on received-signal-strength and time-of-arrival (TOA) with access points (APs) (in contrast to the usual TOA with satellite receivers, used in global navigation satellite systems) [1].Since the usage of mobile systems is limited by their battery life, the power consumption has to be minimised, using simple, but still accurate, algorithms. However, there is a technical compromise between power consumption and the precision of the position estimation.To provide an effective LBS, such as geofencing in crowded shopping centres, the indoor positioning system (IPS) has to supply information with localisation accuracy of under a few metres. However, due to severe multipath environments and the complexities of radio propagation, it is difficult to implement this service in mobile devices with low power consumption and low cost. Practically, to improve the accuracy of TOA estimation between receivers and transmitters, it is necessary to measure very short timing intervals (tens of nanoseconds). This requires the use of high frequency in delay-measurement modules. It increases the power consumption and development complexity.In this Letter, a phase detection algorithm for estimating the position is proposed with a combination of round-trip time (RTT) measurement and frequency downconversion of the carrier, which can have positioning accuracy within 1 m. Moreover, since the low frequency is utilised by results of the frequency downconversion with a mixer, the power consumption can be reduced on estimation of the distance. In addition, it is simple to implement the proposed algorithm by reuse of the conventional signal processing blocks.In this Letter, a phase detection algorithm for position estimation is proposed with a combination of RTT measurement and the quadrature modulation technique that can have a positioning accuracy of 1...

As state-of-the-art mobile devices are demanded for high performance and attractive designs, system-on-chips have been integrated with many functional blocks into a single chip to reduce the chip size, cost, and power consumption. In this paper, to reduce power consumption of heterogeneous processor, a power management algorithm is proposed with a time-based power control architecture which autonomously performs voltage/clock scaling operations without the intervention of the processors. The proposed algorithm has adaptively adjusted time-threshold levels for voltage/clock control to minimize the power consumption and work in severe time-constraints for real-time processing. The real-time adjustment makes robust performance of the power consumption guarantee regardless of patterns of data traffic and diverse application programs. To show performance of the proposed, they are adopted to an application processor integrated with a communication processor for smartphones. Via electronic system-level simulation, it is shown that the proposed algorithm reduces the power consumption by approximately 40%.

An architecture is proposed to design a single chip with an application processor (AP) and a modem processor (MP). As an aggressive challenge, the MP's dedicated memory is removed to share the main memory with the AP. In addition, an autonomous power management (APM) is presented to reduce the power consumption of time-constrained tasks such as wireless communication. The APM is designed without the intervention of the microprocessors, to deal with the random and sparse data pattern of voice communication. For the architectural exploration, an electronic system-level simulation is performed for verifying the performance and power consumption. Through the simulation results, the proposed architecture exhibits small size, good performance and energy consumption.