Now that it is possible to achieve measurement and control fidelities for individual quantum bits (qubits) above the threshold for fault tolerance, attention is moving towards the difficult task of scaling up the number of physical qubits to the large numbers that are needed for fault-tolerant quantum computing. In this context, quantum-dot-based spin qubits could have substantial advantages over other types of qubit owing to their potential for all-electrical operation and ability to be integrated at high density onto an industrial platform. Initialization, readout and single- and two-qubit gates have been demonstrated in various quantum-dot-based qubit representations. However, as seen with small-scale demonstrations of quantum computers using other types of qubit, combining these elements leads to challenges related to qubit crosstalk, state leakage, calibration and control hardware. Here we overcome these challenges by using carefully designed control techniques to demonstrate a programmable two-qubit quantum processor in a silicon device that can perform the Deutsch-Josza algorithm and the Grover search algorithm-canonical examples of quantum algorithms that outperform their classical analogues. We characterize the entanglement in our processor by using quantum-state tomography of Bell states, measuring state fidelities of 85-89 per cent and concurrences of 73-82 per cent. These results pave the way for larger-scale quantum computers that use spins confined to quantum dots.

Quantum computation requires many qubits that can be coherently controlled and coupled to each other [1]. Qubits that are defined using lithographic techniques are often argued to be promising platforms for scalability, since they can be implemented using semiconductor fabrication technology [2][3][4][5]. However, leading solidstate approaches function only at temperatures below 100 mK, where cooling power is extremely limited, and this severely impacts the perspective for practical quantum computation. Recent works on spins in silicon have shown steps towards a platform that can be operated at higher temperatures by demonstrating long spin lifetimes [6], gate-based spin readout [7], and coherent singlespin control [8], but the crucial two-qubit logic gate has been missing. Here we demonstrate that silicon quantum dots can have sufficient thermal robustness to enable the execution of a universal gate set above one Kelvin. We obtain singlequbit control via electron-spin-resonance (ESR) and readout using Pauli spin blockade. We show individual coherent control of two qubits and measure single-qubit fidelities up to 99.3 %. We demonstrate tunability of the exchange interaction between the two spins from 0.5 up to 18 MHz and use this to execute coherent two-qubit controlled rotations (CROT). The demonstration of 'hot' and universal quantum logic in a semiconductor platform paves the way for quantum integrated circuits hosting the quantum hardware and their control circuitry all on the same chip, providing a scalable approach towards practical quantum information.Spin qubits based on quantum dots are among the most promising candidates for large-scale quantum computation [2,9,10]. Quantum coherence can be maintained in these systems for extremely long times [11] by using isotopically enriched silicon ( 28 Si) as the host material [12]. This has enabled the demonstration of singlequbit control with fidelities exceeding 99.9% [13,14] and the execution of two-qubit logic [15][16][17][18]. The potential to build larger systems with quantum dots manifests in the ability to deterministically engineer and optimize qubit locations and interactions using a technology that greatly resembles today's complementary metal-oxide semiconductor (CMOS) manufacturing. Nonetheless, quantum error correction schemes predict that millions to billions of qubits will be needed for practical quantum informa-tion [19]. Considering that today's devices make use of more than one terminal per qubit [20], wiring up such large systems remains a formidable task. In order to avoid an interconnect bottleneck, quantum integrated circuits hosting the qubits and their electronic control on the same chip have been proposed [2,3,21]. While these architectures provide an elegant way to increase the qubit count to large numbers by leveraging the success of classical integrated circuits, a key question is whether the qubits will be robust against the thermal noise imposed by the power dissipation of the electronics. Demonstrating a universal gate set at elevat...

Electrons and holes confined in quantum dots define an excellent building block for quantum emergence, simulation, and computation. In order for quantum electronics to become practical, large numbers of quantum dots will be required, necessitating the fabrication of scaled structures such as linear and 2D arrays. Group IV semiconductors contain stable isotopes with zero nuclear spin and can thereby serve as excellent host for spins with long quantum coherence. Here we demonstrate group IV quantum dot arrays in silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe) and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temperature budget and Ge/SiGe can make ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N+1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive cross talk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. These results constitute an excellent base for quantum computation with quantum dots and provide opportunities for each platform to be integrated with standard semiconductor manufacturing. * Corresponding Author: m.veldhorst@tudelft.nl arXiv:1909.06575v1 [cond-mat.mes-hall]