SiGe (C)/Si(C) multiquantum wells have been studied as a thermistor material for future bolometers. A thermistor material for uncooled Si-based thermal detectors with thermal coefficient of resistance of 4.5%/K for 100×100 μm2 pixel sizes and low noise constant (K1/f) value of 4.4×10−15 is presented. The outstanding performance of the devices is due to Ni-silicide contacts, smooth interfaces, and high quality multiquantum wells containing high Ge content.
This paper reports on the realization and characterization of the very first quantum-well (QW) mono-crystalline Si/SiGe 18x18 pixel infrared bolometer arrays that are manufactured using IC compatible heterogeneous 3D integration on fan-out wafers. This integration process enables bolometer materials on top of CMOS-based integrated circuits that can not be integrated with conventional monolithic deposition techniques. The manufactured bolometer arrays have a negative temperature coefficient of resistance (TCR) of 2.8%/K. Measurements of the 1/f noise showed a higher value than expected for the bolometers. This result can be compared to lower values of noise achieved for samples of the thermistor material and is believed to result from imperfect metal contacts.
Most of today's commercial solutions for un-cooled IR imaging sensors are based on resistive bolometers using either Vanadium oxide (VOx) or amorphous Silicon (a-Si) as the thermistor material. Despite the long history for both concepts, market penetration outside high-end applications is still limited. By allowing actors in adjacent fields, such as those from the MEMS industry, to enter the market, this situation could change. This requires, however, that technologies fitting their tools and processes are developed. Heterogeneous integration of Si/SiGe quantum well bolometers on standard CMOS read out circuits is one approach that could easily be adopted by the MEMS industry. Due to its mono crystalline nature, the Si/SiGe thermistor material has excellent noise properties that result in a state-ofthe-art signal-to-noise ratio. The material is also stable at temperatures well above 450°C which offers great flexibility for both sensor integration and novel vacuum packaging concepts. We have previously reported on heterogeneous integration of Si/SiGe quantum well bolometers with pitches of 40µm x 40µm and 25µm x 25µm. The technology scales well to smaller pixel pitches and in this paper, we will report on our work on developing heterogeneous integration for Si/SiGe QW bolometers with a pixel pitch of 17µm x 17µm.
Cost efficient integration technologies and materials for manufacturing of uncooled infrared bolometer focal plane arrays (FPA) are presented. The technology platform enables 320x240 pixel resolution with a pitch down to 20 µm and very low NETD.A heterogeneous 3D MEMS integration technology called SOIC (Silicon-On-Integrated-Circuit) is used to combine high performance Si/SiGe bolometers with state-of-the-art electronic read-out-integrated-circuits. The SOIC integration process consists of: (a) Separate fabrication of the CMOS wafer and the MEMS wafer. (b) Adhesive wafer bonding. (c) Sacrificial removal of the MEMS handle wafer. (d) Via-hole etching. (e) Via formation and MEMS device definition. (f) Sacrificial etching of the polymer adhesive.We will present an optimized process flow that only contains dry etch processes for the critical process steps. Thus, extremely small, sub-micrometer feature sizes and vias can be implemented for the infrared bolometer arrays.The Si/SiGe thermistor is grown epitaxially, forming a mono-crystalline multi layer structure. The temperature coefficient of resistance (TCR) is primarily controlled by the concentration of Ge present in the strained SiGe layers. TCR values of more than 3%/K can be achieved with a low signal-to-noise ratio due to the mono-crystalline nature of the material. In addition to its excellent electrical properties, the thermistor material is thermally stable up to temperatures above 600 °C, thus enabling the novel integration and packaging techniques described in this paper. Vacuum sealing at the wafer level reduces the overall costs compared to encapsulation after die singulation. Wafer bonding is performed using a Cu-Sn based metallic bonding process followed by getter activation at ≥350 °C achieving a pressure in the 0.001 mbar range. After assembling, the final metal phases are stable and fully compatible with hightemperature processes. Hermeticity over the product lifetime is accomplished by well-controlled electro-deposition of metal layers, optimized bonding parameters and a suitable bond frame design.
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