With the increasing clock frequencies to multiple Gigahertz and increasing need to achieve it at lower voltages for keeping operating power lower, frequency of operation is not only limited by the datapath delay scaling but also by the behavior of clock signals. Failures induced by violation of minimum clock pulse width required, at higher frequencies is more commonly seen due to increased operating frequencies and usage of voltage scaling techniques for achieving higher frequencies [1]. Silicon failures caused by minimum pulse width violation due to clock shrinkage can be due to variety of reasons right from duty cycle distortion at clock generator (PLL) to clock pulse distortion due to slew degradation along the clock path. In this paper authors discuss different techniques that enable us to minimize pulse width failures as the mechanism that limit the frequency of operation of the device. In this paper we propose a simple and novel technique to detect and diagnose pulse width failures. Silicon results from 40nm multi-million gate industrial SoC is presented to indicate the effects of pulse width degradation on performance of the device and to evaluate the effectiveness of the proposed pattern generation technique.
In sub-threshold technology nodes, device failure due to timing related defects (setup & hold timing) is on rise due to extreme process variability and increasing use of voltage scaling techniques for achieving required performance. High coverage using stuck-at fault patterns, which can effectively screen static defects is no longer sufficient to control DPPM (Defective parts per million). High test coverage of timing defects that is induced by process variation is required for controlling DPPM. Lot of work has been done to find the ways to increase the delay test coverage of industrial circuits including the various methods to cover inter-domain clock faults but very little or no work is done on the ways to effectively cover the asynchronous reset paths to the memory registers for timing defects. In this paper we propose a novel methodology that allows us to effectively detect the failures induced by timing defects on asynchronous reset path of the registers. This problem is further complicated by the fact that commercially available ATPG tools are not capable of generating test patterns due to modeling limitations. Results from 45nm industrial multi-million gates design is presented to illustrate the effectiveness of the proposed methodology.
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