Power Analysis and Reduction Techniques for Transition Fault Testing

Agarwal, Khushboo; Vooka, Srinivas; Ravi, S.; Parekhji, Rubin; Gill, A S

doi:10.1109/ats.2008.86

Cited by 12 publications

(2 citation statements)

References 16 publications

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“…Consequently, a wrong test response may be captured in the capture cycle and delivered to the external test equipment (ATE) [5], [6]. Dedicated low capture-power (LCP) aware ATPG causes a significant test pattern count increase with impact on test time and cost [11]. X-filling, a test set post-processing method, is a very successful approach to reduce capture-power by assigning appropriate binary values to unspecified signals (Xbits) in the test cubes such that switching activity in the launch cycle is reduced [12], [13].…”

Section: Introductionmentioning

confidence: 99%

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Kochte¹,

Miyase²,

Wen³

et al. 2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and embedded deterministic test. This work proposes a novel X-filling algorithm for combinational and broadcast-scan-based test compression schemes which have great practical significance. The algorithm ensures compressibility of test cubes using a SAT-based check. Compared to methods based on topological justification, the solution space of the compressed test vector is not pruned early during the search. Thus, this method allows much more precise low-power X-filling of test vectors. Experiments on benchmark and industrial circuits show the applicability to capture-power reduction during scan testing.

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Section: Introductionmentioning

confidence: 99%

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Kochte¹,

Miyase²,

Wen³

et al. 2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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show abstract

“…However, LOS can achieve higher fault coverage and a smaller test vector count. Therefore, LOS has advantages in terms of the test quality and test cost [1].…”

Section: Introductionmentioning

confidence: 99%

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

Miyase

Uchinodan

Enokimoto

et al. 2011

2011 Asian Test Symposium

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It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC'99 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill.

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Test Strategies for Gated Clock Designs

Keller

Chakravadhanula

2009

Power-Aware Testing and Test Strategies for Low Power Devices

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Power Analysis and Reduction Techniques for Transition Fault Testing

Cited by 12 publications

References 16 publications

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

Test Strategies for Gated Clock Designs

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