A Silicon Testing Strategy for Pulse-Width Failures

Abstract

With the increasing clock frequencies to multiple Gigahertz and increasing need to achieve it at lower voltages for keeping operating power lower, frequency of operation is not only limited by the datapath delay scaling but also by the behavior of clock signals. Failures induced by violation of minimum clock pulse width required, at higher frequencies is more commonly seen due to increased operating frequencies and usage of voltage scaling techniques for achieving higher frequencies [1]. Silicon failures caused by minimum pulse width violation due to clock shrinkage can be due to variety of reasons right from duty cycle distortion at clock generator (PLL) to clock pulse distortion due to slew degradation along the clock path. In this paper authors discuss different techniques that enable us to minimize pulse width failures as the mechanism that limit the frequency of operation of the device. In this paper we propose a simple and novel technique to detect and diagnose pulse width failures. Silicon results from 40nm multi-million gate industrial SoC is presented to indicate the effects of pulse width degradation on performance of the device and to evaluate the effectiveness of the proposed pattern generation technique.