Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs

Jain, Sunil K.; Abraham, J.A.; Vooka, Srinivas; Kale, Sumant; Dutta, Amit Kumar; Parekhji, Rubin

doi:10.1109/vlsid.2007.76

Cited by 3 publications

(3 citation statements)

References 21 publications

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“…For commercial on-chip test compression solutions, such as TestKompress T M or DFTCompilerMAX T M , the proposed scheme is easy to implement as the scan enable signal is driven by the tester. On the other hand, selftest solutions, such as LBIST T M [21] or DBIST T M [22], the scan enable signal is generated from the logic BIST controller. As a result, LV Scan signal needs to be driven by the scan enable generated by the logic bist controller.…”

Section: Discussionmentioning

confidence: 99%

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test

Devanathan

Ravikumar

Mehrotra

et al. 2007

2007 IEEE International Test Conference

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In sub-70nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. We propose a Power-Managed Scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. We also discuss some practical implementation challenges that arise when the proposed scheme is employed on industrial designs. Experimental results on benchmark circuits and industrial designs show a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.

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Section: Discussionmentioning

confidence: 99%

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test

Devanathan

Ravikumar

Mehrotra

et al. 2007

2007 IEEE International Test Conference

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“…(iii) It can be easily extended to support both production self-test and field self-test The DBIST scan compression block diagram is shown in Figure 5. A few specific implementation techniques have contributed to tester TDV and TAT reduction apart from what is normally obtained using DBIST [13]. (i) Modifications of DBIST controller interface signals to provide internal generation of static signals, and hence restrict the DBIST test interface to the same set of signals as normal scan.…”

Section: Scan Compression In Multi-site Test Modementioning

confidence: 99%

“…In addition, a single ATPG run is used to target transition faults across a large portion of the design across different clock domains. This is possible using the aligned capture technique, which ensures a sequential depth of only two for two at-speed clock pulses in respective clock domains [13,15]. The relative benefits are shown in Table 2.…”

Section: Attaining High Test Coveragementioning

confidence: 99%

DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs

Dutta

Alampaily

Prasanth

et al. 2008

2008 IEEE International Test Conference

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Automotive electronics today is characterased by two requirements. One is the well-known aspect of reliability of the components used to build the system. The other is the increasing need for commoditisation of these systems. These requirements pose the dual challenges of meeting very strict quality goals, while at the same time also adhering to affordable cost goals. Devices designed for one end application often find use in others. Consequently, it is important that these devices be designed and tested in a scaleable manner, wherein the high quality and low cost goals are simultaneously met. In this paper, a case study is presented on a set of recently designed automotive chips at Texas Instruments (India). Illustrations of different techniques are given, together with supporting data. These techniques are generic enough to be adopted and further improvised to enhance test cost and test quality optimisations in a larger class of SOCs as well.

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Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test

Dutta

Shah

Swathi

et al. 2009

2009 15th IEEE International on-Line Testing Symposium

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Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs

Cited by 3 publications

References 21 publications

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test

DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs

Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test

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