This paper proposes a hardware efficient low power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor (CNTFET) technology. The proposed TALU architecture combines Adder-Subtractor and Ex-OR cell in one cell, thereby it reduces number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimized at transistor level with a new pass-transistor logic based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively.
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