CNTFET based design of content addressable memory cells

Murotiya, Sneh Lata; Gupta, Anu

doi:10.1109/iccct.2013.6749593

Cited by 5 publications

(8 citation statements)

References 18 publications

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“…estimate the function of 6T, 8T and 11T bitcells over V DD . Even though the leakage current and static/dynamic powers of 11T bitcell are higher than 8T one (Figures [12][13][14], it has better V data (Figure 11) and succeeds to solve the challenges. Also, its leakage-current and powers are still smaller than 'all 6T bitcells in Table 1' and 'other 8T bitcells in Table 2'.…”

Section: Discussionmentioning

confidence: 99%

“…In recent decades, many efforts have been made by researchers to offer optimum designs for bitcell. They declared that thanks to the CNTs, CNTFETs have been considered as a promising alternative for Complementary Metal Oxide Semiconductors (CMOSs) in low power SRAMs [10–75], however, CNFET fabrication process still has some imperfections, including the presence of metallic carbon nanotubes ( m ‐CNTs), imperfect m ‐CNT removal processes, chirality drift, CNT doping variations, and density fluctuations, etc. [76–79].…”

Section: Introductionmentioning

confidence: 99%

“…Although several studies employed ‘decoupled R/W BLs’ and ‘power‐gating’ techniques, none of them referred to this paperʼs point. If it seems that using 11 Transistors causes some foot‐print problems, you should note that previous works utilised more than 11 Transistors without any problems [12, 13, 15, 19, 20, 23, 28, 33, 58, 68]. The following analysis and simulations are done by HSpice, CNTFET Stanford Model, and Monte‐Carlo Method.…”

Section: Introductionmentioning

confidence: 99%

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Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Shahrabadi

2022

IET Circuits, Devices & Syst

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Recently, several studies were done on SRAM bitcells at different supply‐voltages; upper, near or lower to threshold voltage. To the best of the author's knowledge, none of them discussed at threshold supply‐voltage with proper subthreshold operations and Nano/Pico power‐dissipations, hence this paper decides to investigate challenges and solutions of designing at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ = Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, because this voltage will lead to having lower power consumptions. This research applies power‐gating technique to adjust VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, and also utilises output‐inverter to set Logic 1 at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. Although ‘power‐gating’ and ‘output‐inverter’ were used in other works, this study renders specific points about them. In fact, the ability of power‐gating technique in adjusting VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$ without any instabilities in bitcell operation was not reported before, as well as, the idea of employing output‐inverter in read path for setting Logic‐1 at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. It also proposed SNM% as a useful figure‐of‐merit. The goal of this study is not to present new circuits for bitcell, but is to investigate challenges and solutions of working under ‘VboldDboldD=Vboldtboldh ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}={\mathbf{V}}_{\mathbf{t}\mathbf{h}}$’ which these solutions can lead to having an optimum bitcell.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Shahrabadi

2022

IET Circuits, Devices & Syst

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“…In CNFET-based implementation, number of tubes, pitch, and diameter are the parameters that are designed to achieve optimum result unlike aspect ratios in case of CMOS [2,3,[28][29][30]. In this analysis, unlike conventional op-amp, it is presumed that the current from Q1 directly flows through the drain of Q6 and thus to the load capacitance and the current from Q2 goes indirectly through Q5 and the current mirror consisting of Q7 to Q10.…”

Section: Design Of Folded Cascode Op-amp Using Carbon Nanotube Field mentioning

confidence: 99%

Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier

Bendre

Kureshi²,

Waykole

2018

Journal of Nanotechnology

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Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

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“…Table 2 qualitatively compares the major properties of CAM structures implemented in CMOS and the emerging memory technologies, as discussed above. Other emerging technologies such as phase-change memory (PCM) [48], carbon nanotube field-effect transistors (CNTFETs) [49], [50], multigate transistor technologies such as FinFET, as well as single electron transistors have also been envisioned for CAM realization [51], [52]. Table 3 presents the quantitative comparison of the nano-CAMs in terms of area, speed, energy, and endurance [53].…”

Section: A Types Of Nano-camsmentioning

confidence: 99%

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

Karam

Puri

Ghosh³

et al. 2015

Proc. IEEE

160

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CNTFET based design of content addressable memory cells

Cited by 5 publications

References 18 publications

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

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