Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

Karam, Robert; Puri, Ruchir; Ghosh, Swaroop; Bhunia, Swarup

doi:10.1109/jproc.2015.2434888

Cited by 170 publications

(89 citation statements)

References 87 publications

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“…Approaches to reduce the power consumption in CAMs have targeted primarily two main components: matchline power and searchline power [1,2,[21][22][23][24][25][26][27][28][29][30][31][32]. In most applications, a much larger number of mismatches occur than matches [32], and hence many techniques have been tailored to reduce the mismatch power consumption.…”

Section: Related Workmentioning

confidence: 99%

“…Figure 1 shows the block diagram of our CAM chip. The main components of the CAM chip are: data and clock drivers, row and column address decoding blocks and the CAM core [1,2]. The CAM core consists of a 2D array of CAM cells, with 3D IC implementations in development [3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

“…CAM cells have three main types: NAND, NOR, and Ternary [2]. The primary applications of CAMs lie in Internet Protocol packet classification and forwarding [1,8]. They are also used in translation look-aside buffers, Huffman coding/decoding [2], and also for classifying experimental data in sciences, such as high energy particle physics.…”

Section: Introductionmentioning

confidence: 99%

“…Data is most commonly stored in SRAMs, however, other technologies like RRAM and STTRAM are being explored [1,9,19]. This operation is usually not as timing or power The primary applications of CAMs lie in Internet Protocol packet classification and forwarding [1,8].…”

Section: Introductionmentioning

confidence: 99%

“…Data is most commonly stored in SRAMs, however, other technologies like RRAM and STTRAM are being explored [1,9,19]. This operation is usually not as timing or power critical as the search operation itself, as writes are infrequent in CAMs.…”

Section: Introductionmentioning

confidence: 99%

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Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

Joshi

Ogrenci-Memik

et al. 2018

JLPEA

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Abstract:In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-V dd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-V dd CAM chip along with an exploration of the multi-V dd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-V dd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-V dd design operating over the same voltage range with equivalent noise margin. Our multi-V dd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

Joshi

Ogrenci-Memik

et al. 2018

JLPEA

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In‐Memory Computing with Memristor Content Addressable Memories for Pattern Matching

Graves

Sheng

et al. 2020

Advanced Materials

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The dramatic rise of data‐intensive workloads has revived application‐specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing “in‐memory computation”. However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive—content addressable memory (CAM)—shows great promise for mapping a diverse range of computational models for in‐memory computation, with recent ReRAM–CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing.

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Ferroelectric Transistors for Memory and Neuromorphic Device Applications

Kim

Lee

2023

Advanced Materials

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Because a non-centrosymmetric crystal structure is mandatory for ferroelectric properties, very few materials are classified as ferroelectric. Historically, materials with complex crystal structures, such as BaTiO 3 (BTO), Pb[Zr x Ti 1−x ]O 3 (PZT), and Sr 2 Bi 2 TaO 9 (SBT), have been found to exhibit ferroelectricity. [5][6][7][8][9] Due to their spontaneous polarization, ferroelectric materials are diversely applied in memory devices, actuators, sensors, and energy storage. [1,2,[10][11][12][13] As the polarization state of ferroelectric materials can be regulated by an external electric field and the polarization is retained after the removal of the external electric field, such materials have the potential for applications involving high-performance non volatile memories. [9,14] However, some issues of conventional ferroelectric materials, such as high annealing temperatures, the requirement of noble electrode materials, and the diffusion of elements such as Pb complicate the integration of the previously reported ferroelectric materials into complementary metal-oxide semiconductors (CMOSs). [15][16][17][18] Furthermore, the large dielectric constants of perovskite-based ferroelectrics lead to high depolarization fields; [9,16] thus, the materials have short retention time and exhibit unstable polarization. [9] Additionally, the limited thickness scalability, complex etching process, and fatigue behaviors of perovskite-based ferroelectrics hinder the development of highly scaled ferroelectric devices. [9,18] Thus, semiconductor devices based on ferroelectric materials have limited commercial applications. Since the development of hafnia-based ferroelectrics, ferroelectric hafnia has attracted immense attention toward the development of semiconductor devices. [19][20][21] Compared to perovskite-based ferroelectric materials, hafnia-based ferroelectrics exhibit high scalability, and have high coercive electric fields (E c ) and low dielectric permittivity values, making them suitable for the fabrication of high-performance memory devices. [2,16,20,22] Additionally, hafnia is compatible with Si-based CMOS processes. Due to these advantages, hafnia-based ferroelectrics have been used in next-generation memory devices (such as ferroelectric capacitors, transistors, and tunnel junctions [FTJs]). [22][23][24][25][26] This paper reviews the recent findings and applications of hafnia-based ferroelectrics, highlighting the recent advances in ferroelectric transistors for next-generation memory and neuromorphic Ferroelectric materials have been intensively investigated for highperformance nonvolatile memory devices in the past decades, owing to their nonvolatile polarization characteristics. Ferroelectric memory devices are expected to exhibit lower power consumption and higher speed than conventional memory devices. However, non-complementary metal-oxidesemiconductor (CMOS) compatibility and degradation due to fatigue of traditional perovskite-based ferroelectric materials have hindered the development of high-density...

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Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

Cited by 170 publications

References 87 publications

Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

In‐Memory Computing with Memristor Content Addressable Memories for Pattern Matching

Ferroelectric Transistors for Memory and Neuromorphic Device Applications

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