Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

Murotiya, Sneh Lata; Gupta, Anu

doi:10.1080/00207217.2013.828191

Cited by 39 publications

(42 citation statements)

References 20 publications

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“…Here, decoder design of (Moaiyeri et al, 2011) is used because only unary functions are required for S 1 and S 0 . Since a NAND gate produces the AND operation with an inverted output, the proposed selection logic saves nine inverters compared to its counterpart presented in (Murotiya & Gupta, 2013). It produces active low outputs for all possible combinations of S 1 and S 0 .…”

Section: Proposed Cntfet-based 2-bit Ternary Alu (Talu)mentioning

confidence: 97%

“…The truth table for five arithmetic and four logic operations performed by TALU is shown in Table 2. Compared to the TALU of (Murotiya & Gupta, 2013), the proposed design saves one complete Ex-OR module and performs two more arithmetic operations: increment (INR) and decrement (DEC) by logic 1without adding any extra processing module. Besides, the required logic 1 is generated by using two transistors T1 and T2.…”

Section: Proposed Cntfet-based 2-bit Ternary Alu (Talu)mentioning

confidence: 99%

“…To eliminate resistive load, PCNTFETs are utilized as active loads in circuits proposed by Lin, Kim, & Lombardi, (Lin, Kim, & Lombardi, 2010) and Moaiyeri, doostaregan, & Navi, (Moaiyeri, doostaregan, & Navi, 2011). A CNTFET-based 2-bit ternary arithmetic logic unit (TALU) has also been proposed in (Murotiya & Gupta 2013), which is optimized at architecture as well as at circuit level and leads to a hardware efficient design. Recently, some CNTFET-based ternary arithmetic and logic circuits have been proposed in (Sridharan, Gurindagunta, & Pudi, 2013) and (Vudadha, Phaneendra, Sreehari, & Srinivas, 2012), which outperform the previously presented CMOS and CNTFET-based ternary circuits, and therefore, used for comparison in this paper.…”

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confidence: 99%

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Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

Murotiya

Gupta

2015

International Journal of Electronics

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This paper proposes a hardware efficient low power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor (CNTFET) technology. The proposed TALU architecture combines Adder-Subtractor and Ex-OR cell in one cell, thereby it reduces number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimized at transistor level with a new pass-transistor logic based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively.

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Section: Proposed Cntfet-based 2-bit Ternary Alu (Talu)mentioning

confidence: 97%

Section: Proposed Cntfet-based 2-bit Ternary Alu (Talu)mentioning

confidence: 99%

mentioning

confidence: 99%

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Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

Murotiya

Gupta

2015

International Journal of Electronics

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“…In recent years, many digital circuits for binary logic and multiple-valued logic (MVL) as well as analog circuits have been designed based on CNFETs Raychowdhury et al 2005;Cho et al 2009;Lin et al 2011;Moaiyeri et al 2011;Moaiyeri et al 2012abc;Murotiya et al 2014). * Corresponding author.…”

Section: Introductionmentioning

confidence: 99%

Efficient radix-radders for nanoelectronics

Moaiyeri

Chavoshisani

Jalali

et al. 2015

International Journal of Electronics

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In this study, new design method and efficient designs for radix-r adders are proposed for carbon nanotube FET nanotechnology. This application also investigates the capability of the nanoscale CNFET device for designing high-performance analog circuits. The proposed designs benefit from unique electrical properties of CNFET such as near ideal current voltage characteristics, very high transconductance, high-performance switches and very highperformance and high-gain binary inverters, at nanoscale. Moreover, adjustable threshold voltage and the same mobility of electrons and holes in a CNFET facilitate the design and modification procedures. The proposed design can be considered as an instance of a general adder, capable of adding radix-r digits with high precision. It is noteworthy that very limited number of CNT diameters for designing the proposed adder are needed which enhance the manufacturability. The proposed circuits are designed based on arithmetic relations and are also verified at 32nm feature size using HSPICE and the Stanford standard SPICE model.

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“…When it is 1, the circuit becomes a subtractor. [10][11] The same way as the n-bits Full Adder we can have the following structure …”

Section: Binary Addition -Subtractionmentioning

confidence: 99%

Design of ALU and Code Converter Using Matrix Calculation

Rasolofoson¹

2017

PAMJ

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Arithmetic Logic Unit (ALU) is a fundamental building block of a central processing unit (CPU) in any computing system. The ALU is the hardware that performs logical (and, or, xor) and basic arithmetic (addition, subtraction, multiplication, division) operations. Thus, its construction requires techniques in which the treatment of operands should be consistent with operations rules. In this paper, ALU based on matrix calculation introduced and developed by Raoelina Andriambololona is proposed. These techniques aim to remove illogic and inconsistent appearing in the international writing numeration with the usual rules in arithmetic. We also propose the design of code converters which convert Binary to BCD (Binary Coded Decimal) code and vice versa using matrix calculation.

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Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

Cited by 39 publications

References 20 publications

Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

Efficient radix-radders for nanoelectronics

Design of ALU and Code Converter Using Matrix Calculation

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