A Novel Design of Ternary Full Adder Using CNTFETs

Murotiya, Sneh Lata; Gupta, Anu

doi:10.1007/s13369-014-1350-x

Cited by 21 publications

(12 citation statements)

References 16 publications

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“…The least number of transistors belongs to the new THA. Though the proposed TFA has one more transistor than the one presented in [16], the static TFA is not capable of adding three ‘ 2 ’s. Similar to the previous dynamic TFA [17], it is also based on the assumption that the third input variable, c , never becomes ‘ 2 ’.…”

Section: Simulation Resultsmentioning

confidence: 99%

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From static ternary adders to high‐performance race‐free dynamic ones

Rezaie

Mirzaee

Navi

et al. 2015

J. eng.

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Section: Simulation Resultsmentioning

confidence: 99%

“…Several high‐performance static ternary adders have been proposed in the literature [13–16]. A dynamic ternary full adder (TFA) has been also presented in [17] recently.…”

Section: Introductionmentioning

confidence: 99%

From static ternary adders to high‐performance race‐free dynamic ones

Rezaie

Mirzaee

Navi

et al. 2015

J. eng.

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“…The original ternary adder cell presented in ref. [103] is a partial TFA in which V(Carry = ‘1’) = ½V DD . The first major drawback of this design is that the voltage level of ½V DD is generated internally by a non‐stop voltage division.…”

Section: Selected Ternary Full Addersmentioning

confidence: 99%

“… The partial ternary full adder (TFA) in ref. [103] is simplified in this paper to reach a new partial TFA, where V(Carry = ‘1’) = V DD . …”

Section: Selected Ternary Full Addersmentioning

confidence: 99%

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or V DD . This way, in a single-V DD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. K E Y W O R D Sadders, carbon nanotube field effect transistors, digital arithmetic, multivalued logic, multivalued logic circuits, ternary logicThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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“…The quantum capacitance has a significant force in nanoscale device [6]. The CNTFET-based 8T SRAM cell demonstrates that it provides high stability, low delay and low power, which is better than CNTFET-based 6T SRAM cell as well as CMOS SRAM cell was addressed in [7]. The low power Viterbi decoder is designed with the help of carbon nano tube field effect transistor.…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

Kandasamy¹,

Nagarjuna²,

Vijay³

2017

J. Nano- Electron. Phys.

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This paper proposes the novel low power and area efficient ALU (Arithmetic and Logic Unit) using adder and multiplexers. The adder and multiplexer are realized by using CNTFET (Carbon Nano Tube Field Effect Transistor) A verilog model of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in cadence spice software. The proposed ALU is simulated using Monte carlo simulation at 0.9 sub threshold voltage tested with 45 nm technology for the measurement of power and transistor counts. The power consumption of CNTFET based ALU is found to be 45.67 % better than the existing technologies.

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A Novel Design of Ternary Full Adder Using CNTFETs

Cited by 21 publications

References 16 publications

From static ternary adders to high‐performance race‐free dynamic ones

From static ternary adders to high‐performance race‐free dynamic ones

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

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