Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

Kandasamy, Nehru; Nagarjuna, T.; Vijay, G.

doi:10.21272/jnep.9(4).04018

Cited by 5 publications

(5 citation statements)

References 8 publications

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“…The number of transistors depends on the implementation of the XOR gate. It ranges from 16 T when using 4 Nand gates down to 3 T as proposed in [5] (Fig. 6).…”

Section: A 4 To 2 Decoder Circuitmentioning

confidence: 99%

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Best implementations of quaternary adders

Etiemble

2020

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The implementation of a quaternary 1-digit adder composed of a 2-bit binary adder, quaternary to binary decoders and binary to quaternary encoders is compared with several recent implementations of quaternary adders. This simple implementation outperforms all other implementations using only one power supply. It is equivalent to the best other implementation using three power supplies. The best quaternary adder using a 2-bit binary adder, the interface circuits between quaternary and binary levels are just overhead compared to the binary adder. This result shows that the quaternary approach for adders use more transistors, more chip area and more power dissipation than the corresponding binary ones.

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“…The number of transistors depends on the implementation of the XOR gate. It ranges from 16 T when using 4 Nand gates down to 3 T as proposed in [5] (Fig. 6).…”

Section: A 4 To 2 Decoder Circuitmentioning

confidence: 99%

“…A CNTFET 8 T full adder (Fig. 9) has been presented [5]. This adder doesn't restore levels and using it could raise issues, both for noise margins and switching times due to series of pass transistors.…”

Section: -Digit Quaternary Adder Using a Binary Addermentioning

confidence: 99%

Best implementations of quaternary adders

Etiemble

2020

Preprint

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“…The number of transistors depends on the implementation of the XOR gate. It ranges from 16 T when using 4 Nand gates down to 3 T as proposed in [12].An acceptable value is 9 T, which corresponds to the conventional CMOS implementation used in [13]. This implementation doesn't use pass transistors and has a full swing output.…”

Section: A Quaternary To Binary Interfacesmentioning

confidence: 99%

Comparing quaternary and binary multipliers

Etiemble

2020

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We compare the implementation of a 8x8 bit multiplier with two different implementations of a 4x4 quaternary digit multiplier. Interfacing this binary multiplier with quaternary to binary decoders and binary to quaternary encoders leads to a 4x4 multiplier that outperforms the best direct implementation of a 4x4 quaternary multiplier. The far greater complexity of the 1-digit multipliers and 1-digit adders used in this direct implementation compared to the binary 1-bit multipliers and full adders cannot be compensated by the reduced count of quaternary operators. As the best quaternary multiplier includes the corresponding binary one, it means that there is no opportunity to get less interconnects, less chip area, less power dissipation with the quaternary multiplier.

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“…The overall ternary half adder has a total of 16 + 16 + 16 + 6 + 12 = 66 transistors There are different possible implementations of a binary half adder. A first one is presented in the left part of it is the typical implementation using a Xor gate that can be implemented with 3 transistors as proposed in [10] (Fig. 13).…”

Section: B Addersmentioning

confidence: 99%

“…The multiplexers correspond to the following equations: [10]. Again, this adder doesn't restore levels and using it could raise issues.…”

Section: B Addersmentioning

confidence: 99%

Ternary circuits: why R=3 is not the Optimal Radix for Computation

Etiemble¹

2019

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A demonstration that e=2.718 rounded to 3 is the best radix for computation is disproved. The MOSFET-like CNTFET technology is used to compare inverters, Nand, adders, multipliers, D Flip-Flops and SRAM cells. The transistor count ratio between ternary and binary circuits is generally greater than the log(3)/log(2) information ratio. The only exceptions concern a circuit approach that combines two circuit drawbacks (an additional power supply and a circuit conflict between transistors) and only when it implements circuits based on the ternary inverter. For arithmetic circuits such as adders and multipliers, the ternary circuits are always outperformed by the binary ones using the same technology.

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Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

Cited by 5 publications

References 8 publications

Best implementations of quaternary adders

Best implementations of quaternary adders

Comparing quaternary and binary multipliers

Ternary circuits: why R=3 is not the Optimal Radix for Computation

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