This letter reports the small-signal and large-signal performances at high drain voltage (V DS ) ranging up to 60 V for a 0.5 µm gate length two-dimensional hole gas diamond metal-oxide-semiconductor field-effect transistor with a 100-nm-thick atomic-layer-deposited Al 2 O 3 film on a IIa-type polycrystalline diamond substrate with (110) preferential surfaces. This diamond FET demonstrated a cutoff frequency (f T ) of 31 GHz, indicating that its carrier velocity was reaching 1.0 × 10 7 cm/s for the first time in diamond. In addition, a f T of 24 GHz was obtained at V DS = −60 V, thus giving a f T × V DS product of 1.44 THz•V. This diamond FET is promising for use as a high-frequency transistor under high voltage conditions. Under application of a high voltage, a maximum output power density of 3.8 W/mm (the highest in diamond) with an associated gain and power added efficiency were 11.6 dB and 23.1% was obtained when biased at V DS = −50 V using a load-pull system at 1 GHz.
During selective epitaxial growth of diamond through SiO2 masks, silicon terminations were formed on a diamond surface by replacing oxygen terminations under the masks. The high temperature of selective growth and its reductive atmosphere possibly allowed Si atoms in SiO2 to interact with the diamond surface, resulting in silicon terminated diamond (C–Si diamond) composed of a monolayer or thin multi-layers of carbon and silicon bonds on diamond. Diamond metal oxide semiconductor field effect transistors (MOSFETs), with a C–Si diamond channel and selectively grown undoped or heavily boron-doped (p+) source/drain (S/D) layers, have been fabricated. Both the MOSFETs with undoped and p+ S/D exhibited enhancement mode (normally off) FET characteristics. The drain current (IDS) of the undoped device reached −17 mA/mm with threshold voltage (VT) −19 V; the p+ device attained a high IDS −165 mA/mm with a VT of −6 V being one of the best normally off diamond FETs. Transmission electron microscopy and energy dispersive x-ray spectroscopy confirmed the presence of C–Si diamond under the SiO2 masking area. The field effect mobility and interface state density at the C–Si/SiO2 (220 nm)/Al2O3 (100 nm) MOS capacitor are 102 cm2 V−1 s−1 and 4.6 × 1012 cm−2 eV−1, respectively. The MOSFET operation of C–Si diamond provides an alternative approach for diamond.
This letter reports a column-parallel clock skew self-calibration circuit for time-resolved (TR) CMOS image sensors. In TR CMOS imagers, as the time resolution increases, the skew of gating clock between pixels becomes a difficult problem because the clock skew causes the reduction of measurable maximum range in particular pixels or unmeasurable pixels. To calibrate the skew in short time, a column-parallel skew self-calibration circuit based on two-stage delay line and a dual clock tree is proposed. The experimental results show that the skew calibration circuit successfully reduces the skew from 247 ps rms to 25 ps rms , and the calibration time is only 12 µs, which is much faster than the previous work.
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